ddsc.map.eqn

DDS数字频率合成器

-- Copyright (C) 1991-2006 Altera Corporation
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--E1_q_a[0] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[0]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[0]_PORT_A_address_reg = DFFE(E1_q_a[0]_PORT_A_address, E1_q_a[0]_clock_0, , , );
E1_q_a[0]_clock_0 = clk;
E1_q_a[0]_PORT_A_data_out = MEMORY(, , E1_q_a[0]_PORT_A_address_reg, , , , , , E1_q_a[0]_clock_0, , , , , );
E1_q_a[0] = E1_q_a[0]_PORT_A_data_out[0];


--E1_q_a[1] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[1]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[1]_PORT_A_address_reg = DFFE(E1_q_a[1]_PORT_A_address, E1_q_a[1]_clock_0, , , );
E1_q_a[1]_clock_0 = clk;
E1_q_a[1]_PORT_A_data_out = MEMORY(, , E1_q_a[1]_PORT_A_address_reg, , , , , , E1_q_a[1]_clock_0, , , , , );
E1_q_a[1] = E1_q_a[1]_PORT_A_data_out[0];


--E1_q_a[2] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[2]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[2]_PORT_A_address_reg = DFFE(E1_q_a[2]_PORT_A_address, E1_q_a[2]_clock_0, , , );
E1_q_a[2]_clock_0 = clk;
E1_q_a[2]_PORT_A_data_out = MEMORY(, , E1_q_a[2]_PORT_A_address_reg, , , , , , E1_q_a[2]_clock_0, , , , , );
E1_q_a[2] = E1_q_a[2]_PORT_A_data_out[0];


--E1_q_a[3] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[3]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[3]_PORT_A_address_reg = DFFE(E1_q_a[3]_PORT_A_address, E1_q_a[3]_clock_0, , , );
E1_q_a[3]_clock_0 = clk;
E1_q_a[3]_PORT_A_data_out = MEMORY(, , E1_q_a[3]_PORT_A_address_reg, , , , , , E1_q_a[3]_clock_0, , , , , );
E1_q_a[3] = E1_q_a[3]_PORT_A_data_out[0];


--E1_q_a[4] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[4]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[4]_PORT_A_address_reg = DFFE(E1_q_a[4]_PORT_A_address, E1_q_a[4]_clock_0, , , );
E1_q_a[4]_clock_0 = clk;
E1_q_a[4]_PORT_A_data_out = MEMORY(, , E1_q_a[4]_PORT_A_address_reg, , , , , , E1_q_a[4]_clock_0, , , , , );
E1_q_a[4] = E1_q_a[4]_PORT_A_data_out[0];


--E1_q_a[5] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[5]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[5]_PORT_A_address_reg = DFFE(E1_q_a[5]_PORT_A_address, E1_q_a[5]_clock_0, , , );
E1_q_a[5]_clock_0 = clk;
E1_q_a[5]_PORT_A_data_out = MEMORY(, , E1_q_a[5]_PORT_A_address_reg, , , , , , E1_q_a[5]_clock_0, , , , , );
E1_q_a[5] = E1_q_a[5]_PORT_A_data_out[0];


--E1_q_a[6] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[6]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[6]_PORT_A_address_reg = DFFE(E1_q_a[6]_PORT_A_address, E1_q_a[6]_clock_0, , , );
E1_q_a[6]_clock_0 = clk;
E1_q_a[6]_PORT_A_data_out = MEMORY(, , E1_q_a[6]_PORT_A_address_reg, , , , , , E1_q_a[6]_clock_0, , , , , );
E1_q_a[6] = E1_q_a[6]_PORT_A_data_out[0];


--E1_q_a[7] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[7]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[7]_PORT_A_address_reg = DFFE(E1_q_a[7]_PORT_A_address, E1_q_a[7]_clock_0, , , );
E1_q_a[7]_clock_0 = clk;
E1_q_a[7]_PORT_A_data_out = MEMORY(, , E1_q_a[7]_PORT_A_address_reg, , , , , , E1_q_a[7]_clock_0, , , , , );
E1_q_a[7] = E1_q_a[7]_PORT_A_data_out[0];


--E1_q_a[8] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[8]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[8]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[8]_PORT_A_address_reg = DFFE(E1_q_a[8]_PORT_A_address, E1_q_a[8]_clock_0, , , );
E1_q_a[8]_clock_0 = clk;
E1_q_a[8]_PORT_A_data_out = MEMORY(, , E1_q_a[8]_PORT_A_address_reg, , , , , , E1_q_a[8]_clock_0, , , , , );
E1_q_a[8] = E1_q_a[8]_PORT_A_data_out[0];


--E1_q_a[9] is lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_19p:auto_generated|q_a[9]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Un-registered
E1_q_a[9]_PORT_A_address = BUS(A1L102, A1L104, A1L106, A1L108, A1L110, A1L112, A1L114, A1L116, A1L118, A1L120);
E1_q_a[9]_PORT_A_address_reg = DFFE(E1_q_a[9]_PORT_A_address, E1_q_a[9]_clock_0, , , );
E1_q_a[9]_clock_0 = clk;
E1_q_a[9]_PORT_A_data_out = MEMORY(, , E1_q_a[9]_PORT_A_address_reg, , , , , , E1_q_a[9]_clock_0, , , , , );
E1_q_a[9] = E1_q_a[9]_PORT_A_data_out[0];


--acc[22] is acc[22]
acc[22] = DFFEAS(A1L69, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[2] is phasew[2]
phasew[2] = DFFEAS(phasein[2], clk,  ,  ,  ,  ,  ,  ,  );


--acc[21] is acc[21]
acc[21] = DFFEAS(A1L66, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[1] is phasew[1]
phasew[1] = DFFEAS(phasein[1], clk,  ,  ,  ,  ,  ,  ,  );


--acc[20] is acc[20]
acc[20] = DFFEAS(A1L63, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[0] is phasew[0]
phasew[0] = DFFEAS(phasein[0], clk,  ,  ,  ,  ,  ,  ,  );


--A1L99 is add~503
A1L99 = CARRY(acc[20] & phasew[0]);


--A1L101 is add~505
A1L101 = CARRY(acc[21] & !phasew[1] & !A1L99 # !acc[21] & (!A1L99 # !phasew[1]));


--A1L102 is add~506
A1L102 = (acc[22] $ phasew[2] $ !A1L101) # GND;

--A1L103 is add~507
A1L103 = CARRY(acc[22] & (phasew[2] # !A1L101) # !acc[22] & phasew[2] & !A1L101);


--acc[23] is acc[23]
acc[23] = DFFEAS(A1L72, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[3] is phasew[3]
phasew[3] = DFFEAS(phasein[3], clk,  ,  ,  ,  ,  ,  ,  );


--A1L104 is add~508
A1L104 = acc[23] & (phasew[3] & A1L103 & VCC # !phasew[3] & !A1L103) # !acc[23] & (phasew[3] & !A1L103 # !phasew[3] & (A1L103 # GND));

--A1L105 is add~509
A1L105 = CARRY(acc[23] & !phasew[3] & !A1L103 # !acc[23] & (!A1L103 # !phasew[3]));


--acc[24] is acc[24]
acc[24] = DFFEAS(A1L75, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[4] is phasew[4]
phasew[4] = DFFEAS(phasein[4], clk,  ,  ,  ,  ,  ,  ,  );


--A1L106 is add~510
A1L106 = (acc[24] $ phasew[4] $ !A1L105) # GND;

--A1L107 is add~511
A1L107 = CARRY(acc[24] & (phasew[4] # !A1L105) # !acc[24] & phasew[4] & !A1L105);


--acc[25] is acc[25]
acc[25] = DFFEAS(A1L78, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[5] is phasew[5]
phasew[5] = DFFEAS(phasein[5], clk,  ,  ,  ,  ,  ,  ,  );


--A1L108 is add~512
A1L108 = acc[25] & (phasew[5] & A1L107 & VCC # !phasew[5] & !A1L107) # !acc[25] & (phasew[5] & !A1L107 # !phasew[5] & (A1L107 # GND));

--A1L109 is add~513
A1L109 = CARRY(acc[25] & !phasew[5] & !A1L107 # !acc[25] & (!A1L107 # !phasew[5]));


--acc[26] is acc[26]
acc[26] = DFFEAS(A1L81, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[6] is phasew[6]
phasew[6] = DFFEAS(phasein[6], clk,  ,  ,  ,  ,  ,  ,  );


--A1L110 is add~514
A1L110 = (acc[26] $ phasew[6] $ !A1L109) # GND;

--A1L111 is add~515
A1L111 = CARRY(acc[26] & (phasew[6] # !A1L109) # !acc[26] & phasew[6] & !A1L109);


--acc[27] is acc[27]
acc[27] = DFFEAS(A1L84, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[7] is phasew[7]
phasew[7] = DFFEAS(phasein[7], clk,  ,  ,  ,  ,  ,  ,  );


--A1L112 is add~516
A1L112 = acc[27] & (phasew[7] & A1L111 & VCC # !phasew[7] & !A1L111) # !acc[27] & (phasew[7] & !A1L111 # !phasew[7] & (A1L111 # GND));

--A1L113 is add~517
A1L113 = CARRY(acc[27] & !phasew[7] & !A1L111 # !acc[27] & (!A1L111 # !phasew[7]));


--acc[28] is acc[28]
acc[28] = DFFEAS(A1L87, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[8] is phasew[8]
phasew[8] = DFFEAS(phasein[8], clk,  ,  ,  ,  ,  ,  ,  );


--A1L114 is add~518
A1L114 = (acc[28] $ phasew[8] $ !A1L113) # GND;

--A1L115 is add~519
A1L115 = CARRY(acc[28] & (phasew[8] # !A1L113) # !acc[28] & phasew[8] & !A1L113);


--acc[29] is acc[29]
acc[29] = DFFEAS(A1L90, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[9] is phasew[9]
phasew[9] = DFFEAS(phasein[9], clk,  ,  ,  ,  ,  ,  ,  );


--A1L116 is add~520
A1L116 = acc[29] & (phasew[9] & A1L115 & VCC # !phasew[9] & !A1L115) # !acc[29] & (phasew[9] & !A1L115 # !phasew[9] & (A1L115 # GND));

--A1L117 is add~521
A1L117 = CARRY(acc[29] & !phasew[9] & !A1L115 # !acc[29] & (!A1L115 # !phasew[9]));


--acc[30] is acc[30]
acc[30] = DFFEAS(A1L93, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[10] is phasew[10]
phasew[10] = DFFEAS(phasein[10], clk,  ,  ,  ,  ,  ,  ,  );


--A1L118 is add~522
A1L118 = (acc[30] $ phasew[10] $ !A1L117) # GND;

--A1L119 is add~523
A1L119 = CARRY(acc[30] & (phasew[10] # !A1L117) # !acc[30] & phasew[10] & !A1L117);


--acc[31] is acc[31]
acc[31] = DFFEAS(A1L96, clk,  ,  ,  ,  ,  ,  ,  );


--phasew[11] is phasew[11]
phasew[11] = DFFEAS(phasein[11], clk,  ,  ,  ,  ,  ,  ,  );


--A1L120 is add~524
A1L120 = acc[31] $ phasew[11] $ A1L119;


--freqw[22] is freqw[22]
freqw[22] = DFFEAS(freqin[22], clk,  ,  ,  ,  ,  ,  ,  );


--freqw[21] is freqw[21]
freqw[21] = DFFEAS(freqin[21], clk,  ,  ,  ,  ,  ,  ,  );


--freqw[20] is freqw[20]
freqw[20] = DFFEAS(freqin[20], clk,  ,  ,  ,  ,  ,  ,  );


--acc[19] is acc[19]
acc[19] = DFFEAS(A1L60, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[19] is freqw[19]
freqw[19] = DFFEAS(freqin[19], clk,  ,  ,  ,  ,  ,  ,  );


--acc[18] is acc[18]
acc[18] = DFFEAS(A1L57, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[18] is freqw[18]
freqw[18] = DFFEAS(freqin[18], clk,  ,  ,  ,  ,  ,  ,  );


--acc[17] is acc[17]
acc[17] = DFFEAS(A1L54, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[17] is freqw[17]
freqw[17] = DFFEAS(freqin[17], clk,  ,  ,  ,  ,  ,  ,  );


--acc[16] is acc[16]
acc[16] = DFFEAS(A1L51, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[16] is freqw[16]
freqw[16] = DFFEAS(freqin[16], clk,  ,  ,  ,  ,  ,  ,  );


--acc[15] is acc[15]
acc[15] = DFFEAS(A1L48, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[15] is freqw[15]
freqw[15] = DFFEAS(freqin[15], clk,  ,  ,  ,  ,  ,  ,  );


--acc[14] is acc[14]
acc[14] = DFFEAS(A1L45, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[14] is freqw[14]
freqw[14] = DFFEAS(freqin[14], clk,  ,  ,  ,  ,  ,  ,  );


--acc[13] is acc[13]
acc[13] = DFFEAS(A1L42, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[13] is freqw[13]
freqw[13] = DFFEAS(freqin[13], clk,  ,  ,  ,  ,  ,  ,  );


--acc[12] is acc[12]
acc[12] = DFFEAS(A1L39, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[12] is freqw[12]
freqw[12] = DFFEAS(freqin[12], clk,  ,  ,  ,  ,  ,  ,  );


--acc[11] is acc[11]
acc[11] = DFFEAS(A1L36, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[11] is freqw[11]
freqw[11] = DFFEAS(freqin[11], clk,  ,  ,  ,  ,  ,  ,  );


--acc[10] is acc[10]
acc[10] = DFFEAS(A1L33, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[10] is freqw[10]
freqw[10] = DFFEAS(freqin[10], clk,  ,  ,  ,  ,  ,  ,  );


--acc[9] is acc[9]
acc[9] = DFFEAS(A1L30, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[9] is freqw[9]
freqw[9] = DFFEAS(freqin[9], clk,  ,  ,  ,  ,  ,  ,  );


--acc[8] is acc[8]
acc[8] = DFFEAS(A1L27, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[8] is freqw[8]
freqw[8] = DFFEAS(freqin[8], clk,  ,  ,  ,  ,  ,  ,  );


--acc[7] is acc[7]
acc[7] = DFFEAS(A1L24, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[7] is freqw[7]
freqw[7] = DFFEAS(freqin[7], clk,  ,  ,  ,  ,  ,  ,  );


--acc[6] is acc[6]
acc[6] = DFFEAS(A1L21, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[6] is freqw[6]
freqw[6] = DFFEAS(freqin[6], clk,  ,  ,  ,  ,  ,  ,  );


--acc[5] is acc[5]
acc[5] = DFFEAS(A1L18, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[5] is freqw[5]
freqw[5] = DFFEAS(freqin[5], clk,  ,  ,  ,  ,  ,  ,  );


--acc[4] is acc[4]
acc[4] = DFFEAS(A1L15, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[4] is freqw[4]
freqw[4] = DFFEAS(freqin[4], clk,  ,  ,  ,  ,  ,  ,  );


--acc[3] is acc[3]
acc[3] = DFFEAS(A1L12, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[3] is freqw[3]
freqw[3] = DFFEAS(freqin[3], clk,  ,  ,  ,  ,  ,  ,  );


--acc[2] is acc[2]
acc[2] = DFFEAS(A1L9, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[2] is freqw[2]
freqw[2] = DFFEAS(freqin[2], clk,  ,  ,  ,  ,  ,  ,  );


--acc[1] is acc[1]
acc[1] = DFFEAS(A1L6, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[1] is freqw[1]
freqw[1] = DFFEAS(freqin[1], clk,  ,  ,  ,  ,  ,  ,  );


--acc[0] is acc[0]
acc[0] = DFFEAS(A1L3, clk,  ,  ,  ,  ,  ,  ,  );


--freqw[0] is freqw[0]
freqw[0] = DFFEAS(freqin[0], clk,  ,  ,  ,  ,  ,  ,  );


--A1L3 is acc[0]~256
A1L3 = acc[0] & (freqw[0] $ VCC) # !acc[0] & freqw[0] & VCC;

--A1L4 is acc[0]~257
A1L4 = CARRY(acc[0] & freqw[0]);


--A1L6 is acc[1]~258
A1L6 = acc[1] & (freqw[1] & A1L4 & VCC # !freqw[1] & !A1L4) # !acc[1] & (freqw[1] & !A1L4 # !freqw[1] & (A1L4 # GND));

--A1L7 is acc[1]~259
A1L7 = CARRY(acc[1] & !freqw[1] & !A1L4 # !acc[1] & (!A1L4 # !freqw[1]));


--A1L9 is acc[2]~260
A1L9 = (acc[2] $ freqw[2] $ !A1L7) # GND;

--A1L10 is acc[2]~261
A1L10 = CARRY(acc[2] & (freqw[2] # !A1L7) # !acc[2] & freqw[2] & !A1L7);


--A1L12 is acc[3]~262
A1L12 = acc[3] & (freqw[3] & A1L10 & VCC # !freqw[3] & !A1L10) # !acc[3] & (freqw[3] & !A1L10 # !freqw[3] & (A1L10 # GND));

--A1L13 is acc[3]~263
A1L13 = CARRY(acc[3] & !freqw[3] & !A1L10 # !acc[3] & (!A1L10 # !freqw[3]));


--A1L15 is acc[4]~264
A1L15 = (acc[4] $ freqw[4] $ !A1L13) # GND;

--A1L16 is acc[4]~265
A1L16 = CARRY(acc[4] & (freqw[4] # !A1L13) # !acc[4] & freqw[4] & !A1L13);


--A1L18 is acc[5]~266
A1L18 = acc[5] & (freqw[5] & A1L16 & VCC # !freqw[5] & !A1L16) # !acc[5] & (freqw[5] & !A1L16 # !freqw[5] & (A1L16 # GND));

--A1L19 is acc[5]~267
A1L19 = CARRY(acc[5] & !freqw[5] & !A1L16 # !acc[5] & (!A1L16 # !freqw[5]));


--A1L21 is acc[6]~268
A1L21 = (acc[6] $ freqw[6] $ !A1L19) # GND;

--A1L22 is acc[6]~269
A1L22 = CARRY(acc[6] & (freqw[6] # !A1L19) # !acc[6] & freqw[6] & !A1L19);


--A1L24 is acc[7]~270
A1L24 = acc[7] & (freqw[7] & A1L22 & VCC # !freqw[7] & !A1L22) # !acc[7] & (freqw[7] & !A1L22 # !freqw[7] & (A1L22 # GND));

--A1L25 is acc[7]~271
A1L25 = CARRY(acc[7] & !freqw[7] & !A1L22 # !acc[7] & (!A1L22 # !freqw[7]));