mgvgi.v

实现简单CPU功能的源码

//lpm_rom INTENDED_DEVICE_FAMILY="FLEX10K" LPM_ADDRESS_CONTROL="REGISTERED" LPM_FILE="rom.mif" LPM_NUMWORDS=256 LPM_OUTDATA="UNREGISTERED" LPM_TYPE="LPM_ROM" LPM_WIDTH=32 LPM_WIDTHAD=8 address inclock q
//VERSION_BEGIN 7.1 cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



// Copyright (C) 1991-2007 Altera Corporation
//  Your use of Altera Corporation's design tools, logic functions 
//  and other software and tools, and its AMPP partner logic 
//  functions, and any output files from any of the foregoing 
//  (including device programming or simulation files), and any 
//  associated documentation or information are expressly subject 
//  to the terms and conditions of the Altera Program License 
//  Subscription Agreement, Altera MegaCore Function License 
//  Agreement, or other applicable license agreement, including, 
//  without limitation, that your use is for the sole purpose of 
//  programming logic devices manufactured by Altera and sold by 
//  Altera or its authorized distributors.  Please refer to the 
//  applicable agreement for further details.



//synthesis_resources = lpm_rom 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  mgvgi
	( 
	address,
	inclock,
	q) /* synthesis synthesis_clearbox=1 */;
	input   [7:0]  address;
	input   inclock;
	output   [31:0]  q;

	wire  [31:0]   wire_mgl_prim1_q;

	lpm_rom   mgl_prim1
	( 
	.address(address),
	.inclock(inclock),
	.q(wire_mgl_prim1_q));
	defparam
		mgl_prim1.lpm_address_control = "REGISTERED",
		mgl_prim1.lpm_file = "rom.mif",
		mgl_prim1.lpm_numwords = 256,
		mgl_prim1.lpm_outdata = "UNREGISTERED",
		mgl_prim1.lpm_type = "LPM_ROM",
		mgl_prim1.lpm_width = 32,
		mgl_prim1.lpm_widthad = 8;
	assign
		q = wire_mgl_prim1_q;
endmodule //mgvgi
//VALID FILE