mg5eh.hier_info

来自「实现简单CPU功能的源码」· HIER_INFO 代码 · 共 417 行

|mg5eh
address[0] => address[0]~7.IN1
address[1] => address[1]~6.IN1
address[2] => address[2]~5.IN1
address[3] => address[3]~4.IN1
address[4] => address[4]~3.IN1
address[5] => address[5]~2.IN1
address[6] => address[6]~1.IN1
address[7] => address[7]~0.IN1
data[0] => data[0]~15.IN1
data[1] => data[1]~14.IN1
data[2] => data[2]~13.IN1
data[3] => data[3]~12.IN1
data[4] => data[4]~11.IN1
data[5] => data[5]~10.IN1
data[6] => data[6]~9.IN1
data[7] => data[7]~8.IN1
data[8] => data[8]~7.IN1
data[9] => data[9]~6.IN1
data[10] => data[10]~5.IN1
data[11] => data[11]~4.IN1
data[12] => data[12]~3.IN1
data[13] => data[13]~2.IN1
data[14] => data[14]~1.IN1
data[15] => data[15]~0.IN1
inclock => inclock~0.IN1
q[0] <= lpm_ram_dq:mgl_prim1.q
q[1] <= lpm_ram_dq:mgl_prim1.q
q[2] <= lpm_ram_dq:mgl_prim1.q
q[3] <= lpm_ram_dq:mgl_prim1.q
q[4] <= lpm_ram_dq:mgl_prim1.q
q[5] <= lpm_ram_dq:mgl_prim1.q
q[6] <= lpm_ram_dq:mgl_prim1.q
q[7] <= lpm_ram_dq:mgl_prim1.q
q[8] <= lpm_ram_dq:mgl_prim1.q
q[9] <= lpm_ram_dq:mgl_prim1.q
q[10] <= lpm_ram_dq:mgl_prim1.q
q[11] <= lpm_ram_dq:mgl_prim1.q
q[12] <= lpm_ram_dq:mgl_prim1.q
q[13] <= lpm_ram_dq:mgl_prim1.q
q[14] <= lpm_ram_dq:mgl_prim1.q
q[15] <= lpm_ram_dq:mgl_prim1.q
we => we~0.IN1


|mg5eh|lpm_ram_dq:mgl_prim1
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
data[8] => altram:sram.data[8]
data[9] => altram:sram.data[9]
data[10] => altram:sram.data[10]
data[11] => altram:sram.data[11]
data[12] => altram:sram.data[12]
data[13] => altram:sram.data[13]
data[14] => altram:sram.data[14]
data[15] => altram:sram.data[15]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]
q[8] <= altram:sram.q[8]
q[9] <= altram:sram.q[9]
q[10] <= altram:sram.q[10]
q[11] <= altram:sram.q[11]
q[12] <= altram:sram.q[12]
q[13] <= altram:sram.q[13]
q[14] <= altram:sram.q[14]
q[15] <= altram:sram.q[15]


|mg5eh|lpm_ram_dq:mgl_prim1|altram:sram
we => segment[0][15].WE
we => segment[0][14].WE
we => segment[0][13].WE
we => segment[0][12].WE
we => segment[0][11].WE
we => segment[0][10].WE
we => segment[0][9].WE
we => segment[0][8].WE
we => segment[0][7].WE
we => segment[0][6].WE
we => segment[0][5].WE
we => segment[0][4].WE
we => segment[0][3].WE
we => segment[0][2].WE
we => segment[0][1].WE
we => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
data[8] => segment[0][8].DATAIN
data[9] => segment[0][9].DATAIN
data[10] => segment[0][10].DATAIN
data[11] => segment[0][11].DATAIN
data[12] => segment[0][12].DATAIN
data[13] => segment[0][13].DATAIN
data[14] => segment[0][14].DATAIN
data[15] => segment[0][15].DATAIN
address[0] => segment[0][15].WADDR
address[0] => segment[0][15].RADDR
address[0] => segment[0][14].WADDR
address[0] => segment[0][14].RADDR
address[0] => segment[0][13].WADDR
address[0] => segment[0][13].RADDR
address[0] => segment[0][12].WADDR
address[0] => segment[0][12].RADDR
address[0] => segment[0][11].WADDR
address[0] => segment[0][11].RADDR
address[0] => segment[0][10].WADDR
address[0] => segment[0][10].RADDR
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][15].WADDR1
address[1] => segment[0][15].RADDR1
address[1] => segment[0][14].WADDR1
address[1] => segment[0][14].RADDR1
address[1] => segment[0][13].WADDR1
address[1] => segment[0][13].RADDR1
address[1] => segment[0][12].WADDR1
address[1] => segment[0][12].RADDR1
address[1] => segment[0][11].WADDR1
address[1] => segment[0][11].RADDR1
address[1] => segment[0][10].WADDR1
address[1] => segment[0][10].RADDR1
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][15].WADDR2
address[2] => segment[0][15].RADDR2
address[2] => segment[0][14].WADDR2
address[2] => segment[0][14].RADDR2
address[2] => segment[0][13].WADDR2
address[2] => segment[0][13].RADDR2
address[2] => segment[0][12].WADDR2
address[2] => segment[0][12].RADDR2
address[2] => segment[0][11].WADDR2
address[2] => segment[0][11].RADDR2
address[2] => segment[0][10].WADDR2
address[2] => segment[0][10].RADDR2
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][15].WADDR3
address[3] => segment[0][15].RADDR3
address[3] => segment[0][14].WADDR3
address[3] => segment[0][14].RADDR3
address[3] => segment[0][13].WADDR3
address[3] => segment[0][13].RADDR3
address[3] => segment[0][12].WADDR3
address[3] => segment[0][12].RADDR3
address[3] => segment[0][11].WADDR3
address[3] => segment[0][11].RADDR3
address[3] => segment[0][10].WADDR3
address[3] => segment[0][10].RADDR3
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][15].WADDR4
address[4] => segment[0][15].RADDR4
address[4] => segment[0][14].WADDR4
address[4] => segment[0][14].RADDR4
address[4] => segment[0][13].WADDR4
address[4] => segment[0][13].RADDR4
address[4] => segment[0][12].WADDR4
address[4] => segment[0][12].RADDR4
address[4] => segment[0][11].WADDR4
address[4] => segment[0][11].RADDR4
address[4] => segment[0][10].WADDR4
address[4] => segment[0][10].RADDR4
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][15].WADDR5
address[5] => segment[0][15].RADDR5
address[5] => segment[0][14].WADDR5
address[5] => segment[0][14].RADDR5
address[5] => segment[0][13].WADDR5
address[5] => segment[0][13].RADDR5
address[5] => segment[0][12].WADDR5
address[5] => segment[0][12].RADDR5
address[5] => segment[0][11].WADDR5
address[5] => segment[0][11].RADDR5
address[5] => segment[0][10].WADDR5
address[5] => segment[0][10].RADDR5
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][15].WADDR6
address[6] => segment[0][15].RADDR6
address[6] => segment[0][14].WADDR6
address[6] => segment[0][14].RADDR6
address[6] => segment[0][13].WADDR6
address[6] => segment[0][13].RADDR6
address[6] => segment[0][12].WADDR6
address[6] => segment[0][12].RADDR6
address[6] => segment[0][11].WADDR6
address[6] => segment[0][11].RADDR6
address[6] => segment[0][10].WADDR6
address[6] => segment[0][10].RADDR6
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][15].WADDR7
address[7] => segment[0][15].RADDR7
address[7] => segment[0][14].WADDR7
address[7] => segment[0][14].RADDR7
address[7] => segment[0][13].WADDR7
address[7] => segment[0][13].RADDR7
address[7] => segment[0][12].WADDR7
address[7] => segment[0][12].RADDR7
address[7] => segment[0][11].WADDR7
address[7] => segment[0][11].RADDR7
address[7] => segment[0][10].WADDR7
address[7] => segment[0][10].RADDR7
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => segment[0][15].CLK0
clocki => segment[0][14].CLK0
clocki => segment[0][13].CLK0
clocki => segment[0][12].CLK0
clocki => segment[0][11].CLK0
clocki => segment[0][10].CLK0
clocki => segment[0][9].CLK0
clocki => segment[0][8].CLK0
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => ~NO_FANOUT~
be => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT
q[8] <= segment[0][8].DATAOUT
q[9] <= segment[0][9].DATAOUT
q[10] <= segment[0][10].DATAOUT
q[11] <= segment[0][11].DATAOUT
q[12] <= segment[0][12].DATAOUT
q[13] <= segment[0][13].DATAOUT
q[14] <= segment[0][14].DATAOUT
q[15] <= segment[0][15].DATAOUT