📄 mgb0j.map.rpt
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Analysis & Synthesis report for mgb0j
Fri Apr 25 15:02:00 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Fri Apr 25 15:02:00 2008 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name ; mgb0j ;
; Top-level Entity Name ; mgb0j ;
; Family ; FLEX10K ;
+-----------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------+--------------+---------------+
; Top-level entity name ; mgb0j ; mgb0j ;
; Family name ; FLEX10K ; Stratix II ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------+--------------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+
; D:/CPU/greybox_tmp/mgb0j.v ; yes ; User Verilog HDL File ; D:/CPU/greybox_tmp/mgb0j.v ;
; lpm_rom.tdf ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf ;
; altrom.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/altrom.inc ;
; aglobal71.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/aglobal71.inc ;
; altrom.tdf ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/altrom.tdf ;
; memmodes.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/others/maxplus2/memmodes.inc ;
; lpm_decode.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_mux.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/lpm_mux.inc ;
; altqpram.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/altqpram.inc ;
; altsyncram.inc ; yes ; Megafunction ; f:/program files/quartus2/quartus/libraries/megafunctions/altsyncram.inc ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, Altera MegaCore Function License
Info: Agreement, or other applicable license agreement, including,
Info: without limitation, that your use is for the sole purpose of
Info: programming logic devices manufactured by Altera and sold by
Info: Altera or its authorized distributors. Please refer to the
Info: applicable agreement for further details.
Info: Processing started: Fri Apr 25 15:01:59 2008
Info: Command: quartus_map mgb0j --source=D:\CPU/greybox_tmp/mgb0j.v --family=FLEX10K
Info: Found 1 design units, including 1 entities, in source file mgb0j.v
Info: Found entity 1: mgb0j
Info: Elaborating entity "mgb0j" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf
Info: Found entity 1: lpm_rom
Info: Elaborating entity "lpm_rom" for hierarchy "lpm_rom:mgl_prim1"
Info: Elaborated megafunction instantiation "lpm_rom:mgl_prim1"
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/altrom.tdf
Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "lpm_rom:mgl_prim1|altrom:srom"
Error: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File ../RAM/RAM.mif for ROM instance File: f:/program files/quartus2/quartus/libraries/megafunctions/altrom.tdf Line: 129
Error: Can't elaborate user hierarchy "lpm_rom:mgl_prim1|altrom:srom" File: f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf Line: 54
Info: Elaborated megafunction instantiation "lpm_rom:mgl_prim1|altrom:srom", which is child of megafunction instantiation "lpm_rom:mgl_prim1"
Info: Instantiated megafunction "lpm_rom:mgl_prim1" with the following parameter:
Info: Parameter "lpm_address_control" = "REGISTERED"
Info: Parameter "lpm_file" = "../RAM/RAM.mif"
Info: Parameter "lpm_numwords" = "256"
Info: Parameter "lpm_outdata" = "UNREGISTERED"
Info: Parameter "lpm_type" = "LPM_ROM"
Info: Parameter "lpm_width" = "32"
Info: Parameter "lpm_widthad" = "8"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
Info: Allocated 128 megabytes of memory during processing
Error: Processing ended: Fri Apr 25 15:02:00 2008
Error: Elapsed time: 00:00:01
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