mg8lh_resc.tcl

实现简单CPU功能的源码

load_package report
project_open mg8lh
load_report
set report_panel_name	"Analysis & Synthesis Resource Usage Summary"
set rsc_file 	[open mg8lh.rsc w]

foreach panel_name [get_report_panel_names] {
	if { [string match "*$report_panel_name*" "$panel_name"] } {
		set header_row [get_report_panel_row $panel_name -row 0]
		for { set row 1 } { $row < [get_number_of_rows $panel_name] } { incr row } {
			set row_data [get_report_panel_row $panel_name -row $row]
			for { set col 0 } { $col < [llength $row_data] } {incr col } {
				set field [lindex $row_data $col]
				incr col
				set actual_value [lindex $row_data $col]
				if { $actual_value > 0 } {
					if { [string compare $field "Total DLLs"] == 0 } {
						puts $rsc_file "$actual_value DLL"
					}
					if { [string compare $field "Total PLLs"] == 0 } {
						puts $rsc_file "$actual_value PLL"
					}
					if { [string compare $field "Total memory bits"] == 0 } {
						puts $rsc_file "$actual_value ram_bits"
					}
					if { [string compare $field "SERDES transmitters"] == 0 } {
						puts $rsc_file "$actual_value SERDES TX"
					}
					if { [string compare $field "SERDES receivers"] == 0 } {
						puts $rsc_file "$actual_value SERDES RX"
					}
					if { [string compare $field "DSP block 18-bit elements"] == 0 } {
						puts $rsc_file "$actual_value dsp_18bit"
					}
					if { [string compare $field "DSP block 9-bit elements"] == 0 } {
						puts $rsc_file "$actual_value dsp_9bit"
					}
					if { [string compare $field "Total logic elements"] == 0 } {
						puts $rsc_file "$actual_value lut"
					}
				}
			}
		}
	}
}

unload_report
project_close