mg8lh.v

来自「实现简单CPU功能的源码」· Verilog 代码 · 共 62 行

//lpm_ram_dq LPM_ADDRESS_CONTROL="REGISTERED" LPM_FILE="RAM.mif" LPM_INDATA="UNREGISTERED" LPM_OUTDATA="UNREGISTERED" LPM_TYPE="LPM_RAM_DQ" LPM_WIDTH=16 LPM_WIDTHAD=8 address data inclock q we
//VERSION_BEGIN 7.1 cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463



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//  and other software and tools, and its AMPP partner logic 
//  functions, and any output files from any of the foregoing 
//  (including device programming or simulation files), and any 
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//  to the terms and conditions of the Altera Program License 
//  Subscription Agreement, Altera MegaCore Function License 
//  Agreement, or other applicable license agreement, including, 
//  without limitation, that your use is for the sole purpose of 
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//  applicable agreement for further details.



//synthesis_resources = lpm_ram_dq 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  mg8lh
	( 
	address,
	data,
	inclock,
	q,
	we) /* synthesis synthesis_clearbox=1 */;
	input   [7:0]  address;
	input   [15:0]  data;
	input   inclock;
	output   [15:0]  q;
	input   we;

	wire  [15:0]   wire_mgl_prim1_q;

	lpm_ram_dq   mgl_prim1
	( 
	.address(address),
	.data(data),
	.inclock(inclock),
	.q(wire_mgl_prim1_q),
	.we(we));
	defparam
		mgl_prim1.lpm_address_control = "REGISTERED",
		mgl_prim1.lpm_file = "RAM.mif",
		mgl_prim1.lpm_indata = "UNREGISTERED",
		mgl_prim1.lpm_outdata = "UNREGISTERED",
		mgl_prim1.lpm_type = "LPM_RAM_DQ",
		mgl_prim1.lpm_width = 16,
		mgl_prim1.lpm_widthad = 8;
	assign
		q = wire_mgl_prim1_q;
endmodule //mg8lh
//VALID FILE