mgm0g.map.rpt

实现简单CPU功能的源码

; Total logic elements           ; 0          ;
; Total combinational functions  ; 0          ;
;     -- Total 4-input functions ; 0          ;
;     -- Total 3-input functions ; 0          ;
;     -- Total 2-input functions ; 0          ;
;     -- Total 1-input functions ; 0          ;
;     -- Total 0-input functions ; 0          ;
; Total registers                ; 0          ;
; I/O pins                       ; 42         ;
; Total memory bits              ; 4096       ;
; Maximum fan-out node           ; inclock    ;
; Maximum fan-out                ; 16         ;
; Total fan-out                  ; 192        ;
; Average fan-out                ; 3.31       ;
+--------------------------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                     ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------+--------------+
; |mgm0g                     ; 0 (0)       ; 0            ; 4096        ; 42   ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |mgm0g                                  ; work         ;
;    |lpm_ram_dq:mgl_prim1|  ; 0 (0)       ; 0            ; 4096        ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |mgm0g|lpm_ram_dq:mgl_prim1             ; work         ;
;       |altram:sram|        ; 0 (0)       ; 0            ; 4096        ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |mgm0g|lpm_ram_dq:mgl_prim1|altram:sram ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                 ;
+------------------------------------------+-------------+--------------+--------------+--------------+--------------+------+------+
; Name                                     ; Mode        ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+------------------------------------------+-------------+--------------+--------------+--------------+--------------+------+------+
; lpm_ram_dq:mgl_prim1|altram:sram|content ; Single Port ; 256          ; 16           ; --           ; --           ; 4096 ; none ;
+------------------------------------------+-------------+--------------+--------------+--------------+--------------+------+------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq:mgl_prim1 ;
+------------------------+--------------+---------------------------+
; Parameter Name         ; Value        ; Type                      ;
+------------------------+--------------+---------------------------+
; LPM_WIDTH              ; 16           ; Signed Integer            ;
; LPM_WIDTHAD            ; 8            ; Signed Integer            ;
; LPM_NUMWORDS           ; 256          ; Untyped                   ;
; LPM_INDATA             ; UNREGISTERED ; Untyped                   ;
; LPM_ADDRESS_CONTROL    ; REGISTERED   ; Untyped                   ;
; LPM_OUTDATA            ; UNREGISTERED ; Untyped                   ;
; LPM_FILE               ; UNUSED       ; Untyped                   ;
; USE_EAB                ; ON           ; Untyped                   ;
; DEVICE_FAMILY          ; FLEX10K      ; Untyped                   ;
; CBXI_PARAMETER         ; NOTHING      ; Untyped                   ;
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE            ;
+------------------------+--------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Copyright (C) 1991-2007 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the 
    Info: applicable agreement for further details.
    Info: Processing started: Fri Apr 25 09:59:12 2008
Info: Command: quartus_map mgm0g --source=D:\CPU/greybox_tmp/mgm0g.v --family=FLEX10K
Info: Found 1 design units, including 1 entities, in source file mgm0g.v
    Info: Found entity 1: mgm0g
Info: Elaborating entity "mgm0g" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf
    Info: Found entity 1: lpm_ram_dq
Info: Elaborating entity "lpm_ram_dq" for hierarchy "lpm_ram_dq:mgl_prim1"
Info: Elaborated megafunction instantiation "lpm_ram_dq:mgl_prim1"
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf
    Info: Found entity 1: altram
Info: Elaborating entity "altram" for hierarchy "lpm_ram_dq:mgl_prim1|altram:sram"
Critical Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File D:/CPU/greybox_tmp/none.mif -- setting all initial values to 0
Info: Elaborated megafunction instantiation "lpm_ram_dq:mgl_prim1|altram:sram", which is child of megafunction instantiation "lpm_ram_dq:mgl_prim1"
Info: Instantiated megafunction "lpm_ram_dq:mgl_prim1" with the following parameter:
    Info: Parameter "lpm_address_control" = "REGISTERED"
    Info: Parameter "lpm_indata" = "UNREGISTERED"
    Info: Parameter "lpm_outdata" = "UNREGISTERED"
    Info: Parameter "lpm_type" = "LPM_RAM_DQ"
    Info: Parameter "lpm_width" = "16"
    Info: Parameter "lpm_widthad" = "8"
Info: Implemented 58 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 16 output pins
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 128 megabytes of memory during processing
    Info: Processing ended: Fri Apr 25 09:59:13 2008
    Info: Elapsed time: 00:00:01