cpu.tan.qmsg

来自「实现简单CPU功能的源码」· QMSG 代码 · 共 13 行 · 第 1/2 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "MUL_OUT\[15\]~16 " "Info: Detected gated clock \"MUL_OUT\[15\]~16\" as buffer" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } } { "f:/program files/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/program files/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "MUL_OUT\[15\]~16" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "MUL_OUT\[12\]\$latch MUL_in\[12\] C\[27\] 7.200 ns register " "Info: tsu for register \"MUL_OUT\[12\]\$latch\" (data pin = \"MUL_in\[12\]\", clock pin = \"C\[27\]\") is 7.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.200 ns + Longest pin register " "Info: + Longest pin to register delay is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns MUL_in\[12\] 1 PIN PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'MUL_in\[12\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { MUL_in[12] } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.900 ns) 7.700 ns MUL_OUT\[12\]~77 2 COMB LC6_B20 1 " "Info: 2: + IC(2.700 ns) + CELL(1.900 ns) = 7.700 ns; Loc. = LC6_B20; Fanout = 1; COMB Node = 'MUL_OUT\[12\]~77'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { MUL_in[12] MUL_OUT[12]~77 } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 10.200 ns MUL_OUT\[12\]\$latch 3 REG LC8_B20 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 10.200 ns; Loc. = LC8_B20; Fanout = 1; REG Node = 'MUL_OUT\[12\]\$latch'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { MUL_OUT[12]~77 MUL_OUT[12]$latch } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns ( 67.65 % ) " "Info: Total cell delay = 6.900 ns ( 67.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.300 ns ( 32.35 % ) " "Info: Total interconnect delay = 3.300 ns ( 32.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { MUL_in[12] MUL_OUT[12]~77 MUL_OUT[12]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { MUL_in[12] MUL_in[12]~out MUL_OUT[12]~77 MUL_OUT[12]$latch } { 0.000ns 0.000ns 2.700ns 0.600ns } { 0.000ns 3.100ns 1.900ns 1.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.900 ns + " "Info: + Micro setup delay of destination is 3.900 ns" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C\[27\] destination 6.900 ns - Shortest register " "Info: - Shortest clock path from clock \"C\[27\]\" to destination register is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns C\[27\] 1 CLK PIN_56 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_56; Fanout = 1; CLK Node = 'C\[27\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C[27] } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.400 ns) 4.900 ns MUL_OUT\[15\]~16 2 COMB LC3_B20 16 " "Info: 2: + IC(1.600 ns) + CELL(1.400 ns) = 4.900 ns; Loc. = LC3_B20; Fanout = 16; COMB Node = 'MUL_OUT\[15\]~16'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { C[27] MUL_OUT[15]~16 } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 6.900 ns MUL_OUT\[12\]\$latch 3 REG LC8_B20 1 " "Info: 3: + IC(0.600 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC8_B20; Fanout = 1; REG Node = 'MUL_OUT\[12\]\$latch'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { MUL_OUT[15]~16 MUL_OUT[12]$latch } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.700 ns ( 68.12 % ) " "Info: Total cell delay = 4.700 ns ( 68.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 31.88 % ) " "Info: Total interconnect delay = 2.200 ns ( 31.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { C[27] MUL_OUT[15]~16 MUL_OUT[12]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { C[27] C[27]~out MUL_OUT[15]~16 MUL_OUT[12]$latch } { 0.000ns 0.000ns 1.600ns 0.600ns } { 0.000ns 1.900ns 1.400ns 1.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.200 ns" { MUL_in[12] MUL_OUT[12]~77 MUL_OUT[12]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "10.200 ns" { MUL_in[12] MUL_in[12]~out MUL_OUT[12]~77 MUL_OUT[12]$latch } { 0.000ns 0.000ns 2.700ns 0.600ns } { 0.000ns 3.100ns 1.900ns 1.900ns } "" } } { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { C[27] MUL_OUT[15]~16 MUL_OUT[12]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { C[27] C[27]~out MUL_OUT[15]~16 MUL_OUT[12]$latch } { 0.000ns 0.000ns 1.600ns 0.600ns } { 0.000ns 1.900ns 1.400ns 1.400ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "C\[25\] MUL_OUT\[9\] MUL_OUT\[9\]\$latch 16.200 ns register " "Info: tco from clock \"C\[25\]\" to destination pin \"MUL_OUT\[9\]\" through register \"MUL_OUT\[9\]\$latch\" is 16.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C\[25\] source 10.100 ns + Longest register " "Info: + Longest clock path from clock \"C\[25\]\" to source register is 10.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns C\[25\] 1 CLK PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'C\[25\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C[25] } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.900 ns) 5.400 ns MUL_OUT\[15\]~16 2 COMB LC3_B20 16 " "Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC3_B20; Fanout = 16; COMB Node = 'MUL_OUT\[15\]~16'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { C[25] MUL_OUT[15]~16 } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.400 ns) 10.100 ns MUL_OUT\[9\]\$latch 3 REG LC6_A14 1 " "Info: 3: + IC(3.300 ns) + CELL(1.400 ns) = 10.100 ns; Loc. = LC6_A14; Fanout = 1; REG Node = 'MUL_OUT\[9\]\$latch'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { MUL_OUT[15]~16 MUL_OUT[9]$latch } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 51.49 % ) " "Info: Total cell delay = 5.200 ns ( 51.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 48.51 % ) " "Info: Total interconnect delay = 4.900 ns ( 48.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.100 ns" { C[25] MUL_OUT[15]~16 MUL_OUT[9]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "10.100 ns" { C[25] C[25]~out MUL_OUT[15]~16 MUL_OUT[9]$latch } { 0.000ns 0.000ns 1.600ns 3.300ns } { 0.000ns 1.900ns 1.900ns 1.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register pin " "Info: + Longest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MUL_OUT\[9\]\$latch 1 REG LC6_A14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A14; Fanout = 1; REG Node = 'MUL_OUT\[9\]\$latch'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { MUL_OUT[9]$latch } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 6.100 ns MUL_OUT\[9\] 2 PIN PIN_12 0 " "Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'MUL_OUT\[9\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { MUL_OUT[9]$latch MUL_OUT[9] } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 63.93 % ) " "Info: Total cell delay = 3.900 ns ( 63.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns ( 36.07 % ) " "Info: Total interconnect delay = 2.200 ns ( 36.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { MUL_OUT[9]$latch MUL_OUT[9] } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { MUL_OUT[9]$latch MUL_OUT[9] } { 0.000ns 2.200ns } { 0.000ns 3.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.100 ns" { C[25] MUL_OUT[15]~16 MUL_OUT[9]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "10.100 ns" { C[25] C[25]~out MUL_OUT[15]~16 MUL_OUT[9]$latch } { 0.000ns 0.000ns 1.600ns 3.300ns } { 0.000ns 1.900ns 1.900ns 1.400ns } "" } } { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { MUL_OUT[9]$latch MUL_OUT[9] } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "6.100 ns" { MUL_OUT[9]$latch MUL_OUT[9] } { 0.000ns 2.200ns } { 0.000ns 3.900ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "MUL_OUT\[4\]\$latch C\[25\] C\[25\] 2.500 ns register " "Info: th for register \"MUL_OUT\[4\]\$latch\" (data pin = \"C\[25\]\", clock pin = \"C\[25\]\") is 2.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C\[25\] destination 10.000 ns + Longest register " "Info: + Longest clock path from clock \"C\[25\]\" to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns C\[25\] 1 CLK PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'C\[25\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C[25] } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.900 ns) 5.400 ns MUL_OUT\[15\]~16 2 COMB LC3_B20 16 " "Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC3_B20; Fanout = 16; COMB Node = 'MUL_OUT\[15\]~16'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { C[25] MUL_OUT[15]~16 } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.400 ns) 10.000 ns MUL_OUT\[4\]\$latch 3 REG LC3_A19 1 " "Info: 3: + IC(3.200 ns) + CELL(1.400 ns) = 10.000 ns; Loc. = LC3_A19; Fanout = 1; REG Node = 'MUL_OUT\[4\]\$latch'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { MUL_OUT[15]~16 MUL_OUT[4]$latch } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 52.00 % ) " "Info: Total cell delay = 5.200 ns ( 52.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 48.00 % ) " "Info: Total interconnect delay = 4.800 ns ( 48.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { C[25] MUL_OUT[15]~16 MUL_OUT[4]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { C[25] C[25]~out MUL_OUT[15]~16 MUL_OUT[4]$latch } { 0.000ns 0.000ns 1.600ns 3.200ns } { 0.000ns 1.900ns 1.900ns 1.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns C\[25\] 1 CLK PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'C\[25\]'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { C[25] } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.400 ns) 5.000 ns MUL_OUT\[4\]~69 2 COMB LC1_A19 1 " "Info: 2: + IC(1.700 ns) + CELL(1.400 ns) = 5.000 ns; Loc. = LC1_A19; Fanout = 1; COMB Node = 'MUL_OUT\[4\]~69'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { C[25] MUL_OUT[4]~69 } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 7.500 ns MUL_OUT\[4\]\$latch 3 REG LC3_A19 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.500 ns; Loc. = LC3_A19; Fanout = 1; REG Node = 'MUL_OUT\[4\]\$latch'" {  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { MUL_OUT[4]~69 MUL_OUT[4]$latch } "NODE_NAME" } } { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 69.33 % ) " "Info: Total cell delay = 5.200 ns ( 69.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 30.67 % ) " "Info: Total interconnect delay = 2.300 ns ( 30.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { C[25] MUL_OUT[4]~69 MUL_OUT[4]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { C[25] C[25]~out MUL_OUT[4]~69 MUL_OUT[4]$latch } { 0.000ns 0.000ns 1.700ns 0.600ns } { 0.000ns 1.900ns 1.400ns 1.900ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { C[25] MUL_OUT[15]~16 MUL_OUT[4]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { C[25] C[25]~out MUL_OUT[15]~16 MUL_OUT[4]$latch } { 0.000ns 0.000ns 1.600ns 3.200ns } { 0.000ns 1.900ns 1.900ns 1.400ns } "" } } { "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/program files/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.500 ns" { C[25] MUL_OUT[4]~69 MUL_OUT[4]$latch } "NODE_NAME" } } { "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/quartus2/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { C[25] C[25]~out MUL_OUT[4]~69 MUL_OUT[4]$latch } { 0.000ns 0.000ns 1.700ns 0.600ns } { 0.000ns 1.900ns 1.400ns 1.900ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 19 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "105 " "Info: Allocated 105 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 27 13:05:15 2008 " "Info: Processing ended: Sun Apr 27 13:05:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}