cpu.tan.qmsg

来自「实现简单CPU功能的源码」· QMSG 代码 · 共 13 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 27 13:05:15 2008 " "Info: Processing started: Sun Apr 27 13:05:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off CPU -c CPU " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CPU -c CPU" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[0\]\$latch " "Warning: Node \"MUL_OUT\[0\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[1\]\$latch " "Warning: Node \"MUL_OUT\[1\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[2\]\$latch " "Warning: Node \"MUL_OUT\[2\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[3\]\$latch " "Warning: Node \"MUL_OUT\[3\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[4\]\$latch " "Warning: Node \"MUL_OUT\[4\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[5\]\$latch " "Warning: Node \"MUL_OUT\[5\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[6\]\$latch " "Warning: Node \"MUL_OUT\[6\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[7\]\$latch " "Warning: Node \"MUL_OUT\[7\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[8\]\$latch " "Warning: Node \"MUL_OUT\[8\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[9\]\$latch " "Warning: Node \"MUL_OUT\[9\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[10\]\$latch " "Warning: Node \"MUL_OUT\[10\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[11\]\$latch " "Warning: Node \"MUL_OUT\[11\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[12\]\$latch " "Warning: Node \"MUL_OUT\[12\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[13\]\$latch " "Warning: Node \"MUL_OUT\[13\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[14\]\$latch " "Warning: Node \"MUL_OUT\[14\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MUL_OUT\[15\]\$latch " "Warning: Node \"MUL_OUT\[15\]\$latch\" is a latch" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "C\[27\] " "Info: Assuming node \"C\[27\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "C\[25\] " "Info: Assuming node \"C\[25\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}