cpu.map.qmsg

来自「实现简单CPU功能的源码」· QMSG 代码 · 共 108 行 · 第 1/5 页

{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs ALU:inst5\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 16 " "Info: Parameter \"LPM_WIDTH\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ALU:inst5\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\"" {  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_add_sub:Add1\|addcore:adder ALU:inst5\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\|addcore:adder\", which is child of megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 17 " "Info: Parameter \"LPM_WIDTH\" = \"17\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node ALU:inst5\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 17 " "Info: Parameter \"LPM_WIDTH\" = \"17\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node ALU:inst5\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 17 " "Info: Parameter \"LPM_WIDTH\" = \"17\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs ALU:inst5\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 17 " "Info: Parameter \"LPM_WIDTH\" = \"17\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[7\] C:inst9\|address_out\[7\] " "Info: Duplicate register \"C:inst9\|address\[7\]\" merged to single register \"C:inst9\|address_out\[7\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[6\] C:inst9\|address_out\[6\] " "Info: Duplicate register \"C:inst9\|address\[6\]\" merged to single register \"C:inst9\|address_out\[6\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[5\] C:inst9\|address_out\[5\] " "Info: Duplicate register \"C:inst9\|address\[5\]\" merged to single register \"C:inst9\|address_out\[5\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[4\] C:inst9\|address_out\[4\] " "Info: Duplicate register \"C:inst9\|address\[4\]\" merged to single register \"C:inst9\|address_out\[4\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[3\] C:inst9\|address_out\[3\] " "Info: Duplicate register \"C:inst9\|address\[3\]\" merged to single register \"C:inst9\|address_out\[3\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[2\] C:inst9\|address_out\[2\] " "Info: Duplicate register \"C:inst9\|address\[2\]\" merged to single register \"C:inst9\|address_out\[2\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[1\] C:inst9\|address_out\[1\] " "Info: Duplicate register \"C:inst9\|address\[1\]\" merged to single register \"C:inst9\|address_out\[1\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "C:inst9\|address\[0\] C:inst9\|address_out\[0\] " "Info: Duplicate register \"C:inst9\|address\[0\]\" merged to single register \"C:inst9\|address_out\[0\]\"" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 18 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|addcore:adder ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|addcore:adder\", which is child of megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|addcore:adder\|a_csnbuffer:oflow_node ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\"" {  } { { "addcore.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|addcore:adder\|a_csnbuffer:result_node ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\"" {  } { { "addcore.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 32 " "Info: Parameter \"LPM_WIDTH\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|altshift:result_ext_latency_ffs ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"ALU:inst5\|lpm_mult:Mult0\|mult_tj01:auto_generated\|lpm_add_sub:op_1\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartu