cpu.hier_info

来自「实现简单CPU功能的源码」· HIER_INFO 代码 · 共 1,939 行 · 第 1/5 页

address[5] => segment[0][15].WADDR5
address[5] => segment[0][15].RADDR5
address[5] => segment[0][14].WADDR5
address[5] => segment[0][14].RADDR5
address[5] => segment[0][13].WADDR5
address[5] => segment[0][13].RADDR5
address[5] => segment[0][12].WADDR5
address[5] => segment[0][12].RADDR5
address[5] => segment[0][11].WADDR5
address[5] => segment[0][11].RADDR5
address[5] => segment[0][10].WADDR5
address[5] => segment[0][10].RADDR5
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][15].WADDR6
address[6] => segment[0][15].RADDR6
address[6] => segment[0][14].WADDR6
address[6] => segment[0][14].RADDR6
address[6] => segment[0][13].WADDR6
address[6] => segment[0][13].RADDR6
address[6] => segment[0][12].WADDR6
address[6] => segment[0][12].RADDR6
address[6] => segment[0][11].WADDR6
address[6] => segment[0][11].RADDR6
address[6] => segment[0][10].WADDR6
address[6] => segment[0][10].RADDR6
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][15].WADDR7
address[7] => segment[0][15].RADDR7
address[7] => segment[0][14].WADDR7
address[7] => segment[0][14].RADDR7
address[7] => segment[0][13].WADDR7
address[7] => segment[0][13].RADDR7
address[7] => segment[0][12].WADDR7
address[7] => segment[0][12].RADDR7
address[7] => segment[0][11].WADDR7
address[7] => segment[0][11].RADDR7
address[7] => segment[0][10].WADDR7
address[7] => segment[0][10].RADDR7
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => segment[0][15].CLK0
clocki => segment[0][14].CLK0
clocki => segment[0][13].CLK0
clocki => segment[0][12].CLK0
clocki => segment[0][11].CLK0
clocki => segment[0][10].CLK0
clocki => segment[0][9].CLK0
clocki => segment[0][8].CLK0
clocki => segment[0][7].CLK0
clocki => segment[0][6].CLK0
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => ~NO_FANOUT~
be => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT
q[8] <= segment[0][8].DATAOUT
q[9] <= segment[0][9].DATAOUT
q[10] <= segment[0][10].DATAOUT
q[11] <= segment[0][11].DATAOUT
q[12] <= segment[0][12].DATAOUT
q[13] <= segment[0][13].DATAOUT
q[14] <= segment[0][14].DATAOUT
q[15] <= segment[0][15].DATAOUT


|CPU|MAR:inst13
clk => MAR_out[7]~reg0.CLK
clk => MAR_out[6]~reg0.CLK
clk => MAR_out[5]~reg0.CLK
clk => MAR_out[4]~reg0.CLK
clk => MAR_out[3]~reg0.CLK
clk => MAR_out[2]~reg0.CLK
clk => MAR_out[1]~reg0.CLK
clk => MAR_out[0]~reg0.CLK
PC_in[0] => MAR_out~7.DATAB
PC_in[1] => MAR_out~6.DATAB
PC_in[2] => MAR_out~5.DATAB
PC_in[3] => MAR_out~4.DATAB
PC_in[4] => MAR_out~3.DATAB
PC_in[5] => MAR_out~2.DATAB
PC_in[6] => MAR_out~1.DATAB
PC_in[7] => MAR_out~0.DATAB
MBR_in[0] => MAR_out~15.DATAB
MBR_in[1] => MAR_out~14.DATAB
MBR_in[2] => MAR_out~13.DATAB
MBR_in[3] => MAR_out~12.DATAB
MBR_in[4] => MAR_out~11.DATAB
MBR_in[5] => MAR_out~10.DATAB
MBR_in[6] => MAR_out~9.DATAB
MBR_in[7] => MAR_out~8.DATAB
MAR_out[0] <= MAR_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[1] <= MAR_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[2] <= MAR_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[3] <= MAR_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[4] <= MAR_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[5] <= MAR_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[6] <= MAR_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MAR_out[7] <= MAR_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C[0] => ~NO_FANOUT~
C[1] => ~NO_FANOUT~
C[2] => ~NO_FANOUT~
C[3] => ~NO_FANOUT~
C[4] => ~NO_FANOUT~
C[5] => MAR_out~15.OUTPUTSELECT
C[5] => MAR_out~14.OUTPUTSELECT
C[5] => MAR_out~13.OUTPUTSELECT
C[5] => MAR_out~12.OUTPUTSELECT
C[5] => MAR_out~11.OUTPUTSELECT
C[5] => MAR_out~10.OUTPUTSELECT
C[5] => MAR_out~9.OUTPUTSELECT
C[5] => MAR_out~8.OUTPUTSELECT
C[6] => ~NO_FANOUT~
C[7] => ~NO_FANOUT~
C[8] => ~NO_FANOUT~
C[9] => ~NO_FANOUT~
C[10] => MAR_out~7.OUTPUTSELECT
C[10] => MAR_out~6.OUTPUTSELECT
C[10] => MAR_out~5.OUTPUTSELECT
C[10] => MAR_out~4.OUTPUTSELECT
C[10] => MAR_out~3.OUTPUTSELECT
C[10] => MAR_out~2.OUTPUTSELECT
C[10] => MAR_out~1.OUTPUTSELECT
C[10] => MAR_out~0.OUTPUTSELECT
C[11] => ~NO_FANOUT~
C[12] => ~NO_FANOUT~
C[13] => ~NO_FANOUT~
C[14] => ~NO_FANOUT~
C[15] => ~NO_FANOUT~
C[16] => ~NO_FANOUT~
C[17] => ~NO_FANOUT~
C[18] => ~NO_FANOUT~
C[19] => ~NO_FANOUT~
C[20] => ~NO_FANOUT~
C[21] => ~NO_FANOUT~
C[22] => ~NO_FANOUT~
C[23] => ~NO_FANOUT~
C[24] => ~NO_FANOUT~
C[25] => ~NO_FANOUT~
C[26] => ~NO_FANOUT~
C[27] => ~NO_FANOUT~
C[28] => ~NO_FANOUT~
C[29] => ~NO_FANOUT~
C[30] => ~NO_FANOUT~
C[31] => ~NO_FANOUT~


|CPU|PC:inst12
clk => p[7].CLK
clk => p[6].CLK
clk => p[5].CLK
clk => p[4].CLK
clk => p[3].CLK
clk => p[2].CLK
clk => p[1].CLK
clk => p[0].CLK
PC_in[0] => p~15.DATAB
PC_in[1] => p~14.DATAB
PC_in[2] => p~13.DATAB
PC_in[3] => p~12.DATAB
PC_in[4] => p~11.DATAB
PC_in[5] => p~10.DATAB
PC_in[6] => p~9.DATAB
PC_in[7] => p~8.DATAB
PC_out[0] <= p[0].DB_MAX_OUTPUT_PORT_TYPE
PC_out[1] <= p[1].DB_MAX_OUTPUT_PORT_TYPE
PC_out[2] <= p[2].DB_MAX_OUTPUT_PORT_TYPE
PC_out[3] <= p[3].DB_MAX_OUTPUT_PORT_TYPE
PC_out[4] <= p[4].DB_MAX_OUTPUT_PORT_TYPE
PC_out[5] <= p[5].DB_MAX_OUTPUT_PORT_TYPE
PC_out[6] <= p[6].DB_MAX_OUTPUT_PORT_TYPE
PC_out[7] <= p[7].DB_MAX_OUTPUT_PORT_TYPE
C[0] => ~NO_FANOUT~
C[1] => ~NO_FANOUT~
C[2] => ~NO_FANOUT~
C[3] => ~NO_FANOUT~
C[4] => ~NO_FANOUT~
C[5] => ~NO_FANOUT~
C[6] => p~23.OUTPUTSELECT
C[6] => p~22.OUTPUTSELECT
C[6] => p~21.OUTPUTSELECT
C[6] => p~20.OUTPUTSELECT
C[6] => p~19.OUTPUTSELECT
C[6] => p~18.OUTPUTSELECT
C[6] => p~17.OUTPUTSELECT
C[6] => p~16.OUTPUTSELECT
C[7] => ~NO_FANOUT~
C[8] => ~NO_FANOUT~
C[9] => ~NO_FANOUT~
C[10] => ~NO_FANOUT~
C[11] => ~NO_FANOUT~
C[12] => ~NO_FANOUT~
C[13] => ~NO_FANOUT~
C[14] => ~NO_FANOUT~
C[15] => ~NO_FANOUT~
C[16] => ~NO_FANOUT~
C[17] => ~NO_FANOUT~
C[18] => ~NO_FANOUT~
C[19] => p~7.OUTPUTSELECT
C[19] => p~6.OUTPUTSELECT
C[19] => p~5.OUTPUTSELECT
C[19] => p~4.OUTPUTSELECT
C[19] => p~3.OUTPUTSELECT
C[19] => p~2.OUTPUTSELECT
C[19] => p~1.OUTPUTSELECT
C[19] => p~0.OUTPUTSELECT
C[20] => ~NO_FANOUT~
C[21] => ~NO_FANOUT~
C[22] => ~NO_FANOUT~
C[23] => ~NO_FANOUT~
C[24] => p~15.OUTPUTSELECT
C[24] => p~14.OUTPUTSELECT
C[24] => p~13.OUTPUTSELECT
C[24] => p~12.OUTPUTSELECT
C[24] => p~11.OUTPUTSELECT
C[24] => p~10.OUTPUTSELECT
C[24] => p~9.OUTPUTSELECT
C[24] => p~8.OUTPUTSELECT
C[25] => ~NO_FANOUT~
C[26] => ~NO_FANOUT~
C[27] => ~NO_FANOUT~
C[28] => ~NO_FANOUT~
C[29] => ~NO_FANOUT~
C[30] => ~NO_FANOUT~
C[31] => ~NO_FANOUT~


|CPU|change:inst1
clk => ~NO_FANOUT~
MUL_in[0] => MUL_OUT[0]~5.DATAA
MUL_in[1] => MUL_OUT[1]~4.DATAA
MUL_in[2] => MUL_OUT[2]~3.DATAA
MUL_in[3] => MUL_OUT[3]~2.DATAA
MUL_in[4] => MUL_OUT[4]~1.DATAA
MUL_in[5] => MUL_OUT[5]~0.DATAA
MUL_in[6] => MUL_OUT[6]~6.DATAA
MUL_in[7] => MUL_OUT[7]~7.DATAA
MUL_in[8] => MUL_OUT[8]~8.DATAA
MUL_in[9] => MUL_OUT[9]~9.DATAA
MUL_in[10] => MUL_OUT[10]~10.DATAA
MUL_in[11] => MUL_OUT[11]~11.DATAA
MUL_in[12] => MUL_OUT[12]~12.DATAA
MUL_in[13] => MUL_OUT[13]~13.DATAA
MUL_in[14] => MUL_OUT[14]~14.DATAA
MUL_in[15] => MUL_OUT[15]~15.DATAA
MUL_in[16] => MUL_OUT[0]~5.DATAB
MUL_in[17] => MUL_OUT[1]~4.DATAB
MUL_in[18] => MUL_OUT[2]~3.DATAB
MUL_in[19] => MUL_OUT[3]~2.DATAB
MUL_in[20] => MUL_OUT[4]~1.DATAB
MUL_in[21] => MUL_OUT[5]~0.DATAB
MUL_in[22] => MUL_OUT[6]~6.DATAB
MUL_in[23] => MUL_OUT[7]~7.DATAB
MUL_in[24] => MUL_OUT[8]~8.DATAB
MUL_in[25] => MUL_OUT[9]~9.DATAB
MUL_in[26] => MUL_OUT[10]~10.DATAB
MUL_in[27] => MUL_OUT[11]~11.DATAB
MUL_in[28] => MUL_OUT[12]~12.DATAB
MUL_in[29] => MUL_OUT[13]~13.DATAB
MUL_in[30] => MUL_OUT[14]~14.DATAB
MUL_in[31] => MUL_OUT[15]~15.DATAB
C[0] => ~NO_FANOUT~
C[1] => ~NO_FANOUT~
C[2] => ~NO_FANOUT~
C[3] => ~NO_FANOUT~
C[4] => ~NO_FANOUT~
C[5] => ~NO_FANOUT~
C[6] => ~NO_FANOUT~
C[7] => ~NO_FANOUT~
C[8] => ~NO_FANOUT~
C[9] => ~NO_FANOUT~
C[10] => ~NO_FANOUT~
C[11] => ~NO_FANOUT~
C[12] => ~NO_FANOUT~
C[13] => ~NO_FANOUT~
C[14] => ~NO_FANOUT~
C[15] => ~NO_FANOUT~
C[16] => ~NO_FANOUT~
C[17] => ~NO_FANOUT~
C[18] => ~NO_FANOUT~
C[19] => ~NO_FANOUT~
C[20] => ~NO_FANOUT~
C[21] => ~NO_FANOUT~
C[22] => ~NO_FANOUT~
C[23] => ~NO_FANOUT~
C[24] => ~NO_FANOUT~
C[25] => MUL_OUT[15]~16.IN0
C[25] => MUL_OUT[15]~15.OUTPUTSELECT
C[25] => MUL_OUT[14]~14.OUTPUTSELECT
C[25] => MUL_OUT[13]~13.OUTPUTSELECT
C[25] => MUL_OUT[12]~12.OUTPUTSELECT
C[25] => MUL_OUT[11]~11.OUTPUTSELECT
C[25] => MUL_OUT[10]~10.OUTPUTSELECT
C[25] => MUL_OUT[9]~9.OUTPUTSELECT
C[25] => MUL_OUT[8]~8.OUTPUTSELECT
C[25] => MUL_OUT[7]~7.OUTPUTSELECT
C[25] => MUL_OUT[6]~6.OUTPUTSELECT
C[25] => MUL_OUT[5]~0.OUTPUTSELECT
C[25] => MUL_OUT[4]~1.OUTPUTSELECT
C[25] => MUL_OUT[3]~2.OUTPUTSELECT
C[25] => MUL_OUT[2]~3.OUTPUTSELECT
C[25] => MUL_OUT[1]~4.OUTPUTSELECT
C[25] => MUL_OUT[0]~5.OUTPUTSELECT
C[26] => ~NO_FANOUT~
C[27] => MUL_OUT[15]~16.IN1
C[28] => ~NO_FANOUT~
C[29] => ~NO_FANOUT~
C[30] => ~NO_FANOUT~
C[31] => ~NO_FANOUT~
MUL_OUT[0] <= MUL_OUT[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[1] <= MUL_OUT[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[2] <= MUL_OUT[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[3] <= MUL_OUT[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[4] <= MUL_OUT[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[5] <= MUL_OUT[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[6] <= MUL_OUT[6]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[7] <= MUL_OUT[7]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[8] <= MUL_OUT[8]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[9] <= MUL_OUT[9]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[10] <= MUL_OUT[10]$latch.DB_MAX_OUTPUT_PORT_TYPE
MUL_OUT[11] <= MUL_OU