cpu.hier_info

来自「实现简单CPU功能的源码」· HIER_INFO 代码 · 共 1,939 行 · 第 1/5 页

mul_in[7] => MBR_out~8.DATAB
mul_in[8] => MBR_out~7.DATAB
mul_in[9] => MBR_out~6.DATAB
mul_in[10] => MBR_out~5.DATAB
mul_in[11] => MBR_out~4.DATAB
mul_in[12] => MBR_out~3.DATAB
mul_in[13] => MBR_out~2.DATAB
mul_in[14] => MBR_out~1.DATAB
mul_in[15] => MBR_out~0.DATAB
MBR_out[0] <= MBR_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[1] <= MBR_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[2] <= MBR_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[3] <= MBR_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[4] <= MBR_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[5] <= MBR_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[6] <= MBR_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[7] <= MBR_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[8] <= MBR_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[9] <= MBR_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[10] <= MBR_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[11] <= MBR_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[12] <= MBR_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[13] <= MBR_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[14] <= MBR_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
MBR_out[15] <= MBR_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C[0] => ~NO_FANOUT~
C[1] => ~NO_FANOUT~
C[2] => ~NO_FANOUT~
C[3] => MBR_out~47.OUTPUTSELECT
C[3] => MBR_out~46.OUTPUTSELECT
C[3] => MBR_out~45.OUTPUTSELECT
C[3] => MBR_out~44.OUTPUTSELECT
C[3] => MBR_out~43.OUTPUTSELECT
C[3] => MBR_out~42.OUTPUTSELECT
C[3] => MBR_out~41.OUTPUTSELECT
C[3] => MBR_out~40.OUTPUTSELECT
C[3] => MBR_out~39.OUTPUTSELECT
C[3] => MBR_out~38.OUTPUTSELECT
C[3] => MBR_out~37.OUTPUTSELECT
C[3] => MBR_out~36.OUTPUTSELECT
C[3] => MBR_out~35.OUTPUTSELECT
C[3] => MBR_out~34.OUTPUTSELECT
C[3] => MBR_out~33.OUTPUTSELECT
C[3] => MBR_out~32.OUTPUTSELECT
C[4] => ~NO_FANOUT~
C[5] => ~NO_FANOUT~
C[6] => ~NO_FANOUT~
C[7] => ~NO_FANOUT~
C[8] => ~NO_FANOUT~
C[9] => ~NO_FANOUT~
C[10] => ~NO_FANOUT~
C[11] => ~NO_FANOUT~
C[12] => ~NO_FANOUT~
C[13] => ~NO_FANOUT~
C[14] => ~NO_FANOUT~
C[15] => ~NO_FANOUT~
C[16] => ~NO_FANOUT~
C[17] => ~NO_FANOUT~
C[18] => MBR_out~31.OUTPUTSELECT
C[18] => MBR_out~30.OUTPUTSELECT
C[18] => MBR_out~29.OUTPUTSELECT
C[18] => MBR_out~28.OUTPUTSELECT
C[18] => MBR_out~27.OUTPUTSELECT
C[18] => MBR_out~26.OUTPUTSELECT
C[18] => MBR_out~25.OUTPUTSELECT
C[18] => MBR_out~24.OUTPUTSELECT
C[18] => MBR_out~23.OUTPUTSELECT
C[18] => MBR_out~22.OUTPUTSELECT
C[18] => MBR_out~21.OUTPUTSELECT
C[18] => MBR_out~20.OUTPUTSELECT
C[18] => MBR_out~19.OUTPUTSELECT
C[18] => MBR_out~18.OUTPUTSELECT
C[18] => MBR_out~17.OUTPUTSELECT
C[18] => MBR_out~16.OUTPUTSELECT
C[19] => ~NO_FANOUT~
C[20] => ~NO_FANOUT~
C[21] => ~NO_FANOUT~
C[22] => ~NO_FANOUT~
C[23] => ~NO_FANOUT~
C[24] => ~NO_FANOUT~
C[25] => ~NO_FANOUT~
C[26] => MBR_out~15.OUTPUTSELECT
C[26] => MBR_out~14.OUTPUTSELECT
C[26] => MBR_out~13.OUTPUTSELECT
C[26] => MBR_out~12.OUTPUTSELECT
C[26] => MBR_out~11.OUTPUTSELECT
C[26] => MBR_out~10.OUTPUTSELECT
C[26] => MBR_out~9.OUTPUTSELECT
C[26] => MBR_out~8.OUTPUTSELECT
C[26] => MBR_out~7.OUTPUTSELECT
C[26] => MBR_out~6.OUTPUTSELECT
C[26] => MBR_out~5.OUTPUTSELECT
C[26] => MBR_out~4.OUTPUTSELECT
C[26] => MBR_out~3.OUTPUTSELECT
C[26] => MBR_out~2.OUTPUTSELECT
C[26] => MBR_out~1.OUTPUTSELECT
C[26] => MBR_out~0.OUTPUTSELECT
C[27] => ~NO_FANOUT~
C[28] => ~NO_FANOUT~
C[29] => ~NO_FANOUT~
C[30] => ~NO_FANOUT~
C[31] => ~NO_FANOUT~


|CPU|lpm_ram_dq0:inst
address[0] => lpm_ram_dq:lpm_ram_dq_component.address[0]
address[1] => lpm_ram_dq:lpm_ram_dq_component.address[1]
address[2] => lpm_ram_dq:lpm_ram_dq_component.address[2]
address[3] => lpm_ram_dq:lpm_ram_dq_component.address[3]
address[4] => lpm_ram_dq:lpm_ram_dq_component.address[4]
address[5] => lpm_ram_dq:lpm_ram_dq_component.address[5]
address[6] => lpm_ram_dq:lpm_ram_dq_component.address[6]
address[7] => lpm_ram_dq:lpm_ram_dq_component.address[7]
data[0] => lpm_ram_dq:lpm_ram_dq_component.data[0]
data[1] => lpm_ram_dq:lpm_ram_dq_component.data[1]
data[2] => lpm_ram_dq:lpm_ram_dq_component.data[2]
data[3] => lpm_ram_dq:lpm_ram_dq_component.data[3]
data[4] => lpm_ram_dq:lpm_ram_dq_component.data[4]
data[5] => lpm_ram_dq:lpm_ram_dq_component.data[5]
data[6] => lpm_ram_dq:lpm_ram_dq_component.data[6]
data[7] => lpm_ram_dq:lpm_ram_dq_component.data[7]
data[8] => lpm_ram_dq:lpm_ram_dq_component.data[8]
data[9] => lpm_ram_dq:lpm_ram_dq_component.data[9]
data[10] => lpm_ram_dq:lpm_ram_dq_component.data[10]
data[11] => lpm_ram_dq:lpm_ram_dq_component.data[11]
data[12] => lpm_ram_dq:lpm_ram_dq_component.data[12]
data[13] => lpm_ram_dq:lpm_ram_dq_component.data[13]
data[14] => lpm_ram_dq:lpm_ram_dq_component.data[14]
data[15] => lpm_ram_dq:lpm_ram_dq_component.data[15]
inclock => lpm_ram_dq:lpm_ram_dq_component.inclock
we => lpm_ram_dq:lpm_ram_dq_component.we
q[0] <= lpm_ram_dq:lpm_ram_dq_component.q[0]
q[1] <= lpm_ram_dq:lpm_ram_dq_component.q[1]
q[2] <= lpm_ram_dq:lpm_ram_dq_component.q[2]
q[3] <= lpm_ram_dq:lpm_ram_dq_component.q[3]
q[4] <= lpm_ram_dq:lpm_ram_dq_component.q[4]
q[5] <= lpm_ram_dq:lpm_ram_dq_component.q[5]
q[6] <= lpm_ram_dq:lpm_ram_dq_component.q[6]
q[7] <= lpm_ram_dq:lpm_ram_dq_component.q[7]
q[8] <= lpm_ram_dq:lpm_ram_dq_component.q[8]
q[9] <= lpm_ram_dq:lpm_ram_dq_component.q[9]
q[10] <= lpm_ram_dq:lpm_ram_dq_component.q[10]
q[11] <= lpm_ram_dq:lpm_ram_dq_component.q[11]
q[12] <= lpm_ram_dq:lpm_ram_dq_component.q[12]
q[13] <= lpm_ram_dq:lpm_ram_dq_component.q[13]
q[14] <= lpm_ram_dq:lpm_ram_dq_component.q[14]
q[15] <= lpm_ram_dq:lpm_ram_dq_component.q[15]


|CPU|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
data[8] => altram:sram.data[8]
data[9] => altram:sram.data[9]
data[10] => altram:sram.data[10]
data[11] => altram:sram.data[11]
data[12] => altram:sram.data[12]
data[13] => altram:sram.data[13]
data[14] => altram:sram.data[14]
data[15] => altram:sram.data[15]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]
q[8] <= altram:sram.q[8]
q[9] <= altram:sram.q[9]
q[10] <= altram:sram.q[10]
q[11] <= altram:sram.q[11]
q[12] <= altram:sram.q[12]
q[13] <= altram:sram.q[13]
q[14] <= altram:sram.q[14]
q[15] <= altram:sram.q[15]


|CPU|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram
we => segment[0][15].WE
we => segment[0][14].WE
we => segment[0][13].WE
we => segment[0][12].WE
we => segment[0][11].WE
we => segment[0][10].WE
we => segment[0][9].WE
we => segment[0][8].WE
we => segment[0][7].WE
we => segment[0][6].WE
we => segment[0][5].WE
we => segment[0][4].WE
we => segment[0][3].WE
we => segment[0][2].WE
we => segment[0][1].WE
we => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
data[8] => segment[0][8].DATAIN
data[9] => segment[0][9].DATAIN
data[10] => segment[0][10].DATAIN
data[11] => segment[0][11].DATAIN
data[12] => segment[0][12].DATAIN
data[13] => segment[0][13].DATAIN
data[14] => segment[0][14].DATAIN
data[15] => segment[0][15].DATAIN
address[0] => segment[0][15].WADDR
address[0] => segment[0][15].RADDR
address[0] => segment[0][14].WADDR
address[0] => segment[0][14].RADDR
address[0] => segment[0][13].WADDR
address[0] => segment[0][13].RADDR
address[0] => segment[0][12].WADDR
address[0] => segment[0][12].RADDR
address[0] => segment[0][11].WADDR
address[0] => segment[0][11].RADDR
address[0] => segment[0][10].WADDR
address[0] => segment[0][10].RADDR
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][15].WADDR1
address[1] => segment[0][15].RADDR1
address[1] => segment[0][14].WADDR1
address[1] => segment[0][14].RADDR1
address[1] => segment[0][13].WADDR1
address[1] => segment[0][13].RADDR1
address[1] => segment[0][12].WADDR1
address[1] => segment[0][12].RADDR1
address[1] => segment[0][11].WADDR1
address[1] => segment[0][11].RADDR1
address[1] => segment[0][10].WADDR1
address[1] => segment[0][10].RADDR1
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][15].WADDR2
address[2] => segment[0][15].RADDR2
address[2] => segment[0][14].WADDR2
address[2] => segment[0][14].RADDR2
address[2] => segment[0][13].WADDR2
address[2] => segment[0][13].RADDR2
address[2] => segment[0][12].WADDR2
address[2] => segment[0][12].RADDR2
address[2] => segment[0][11].WADDR2
address[2] => segment[0][11].RADDR2
address[2] => segment[0][10].WADDR2
address[2] => segment[0][10].RADDR2
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][15].WADDR3
address[3] => segment[0][15].RADDR3
address[3] => segment[0][14].WADDR3
address[3] => segment[0][14].RADDR3
address[3] => segment[0][13].WADDR3
address[3] => segment[0][13].RADDR3
address[3] => segment[0][12].WADDR3
address[3] => segment[0][12].RADDR3
address[3] => segment[0][11].WADDR3
address[3] => segment[0][11].RADDR3
address[3] => segment[0][10].WADDR3
address[3] => segment[0][10].RADDR3
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][15].WADDR4
address[4] => segment[0][15].RADDR4
address[4] => segment[0][14].WADDR4
address[4] => segment[0][14].RADDR4
address[4] => segment[0][13].WADDR4
address[4] => segment[0][13].RADDR4
address[4] => segment[0][12].WADDR4
address[4] => segment[0][12].RADDR4
address[4] => segment[0][11].WADDR4
address[4] => segment[0][11].RADDR4
address[4] => segment[0][10].WADDR4
address[4] => segment[0][10].RADDR4
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4