cpu.hier_info

来自「实现简单CPU功能的源码」· HIER_INFO 代码 · 共 1,939 行 · 第 1/5 页

address[6] => segment[0][25].WADDR6
address[6] => segment[0][25].RADDR6
address[6] => segment[0][24].WADDR6
address[6] => segment[0][24].RADDR6
address[6] => segment[0][23].WADDR6
address[6] => segment[0][23].RADDR6
address[6] => segment[0][22].WADDR6
address[6] => segment[0][22].RADDR6
address[6] => segment[0][21].WADDR6
address[6] => segment[0][21].RADDR6
address[6] => segment[0][20].WADDR6
address[6] => segment[0][20].RADDR6
address[6] => segment[0][19].WADDR6
address[6] => segment[0][19].RADDR6
address[6] => segment[0][18].WADDR6
address[6] => segment[0][18].RADDR6
address[6] => segment[0][17].WADDR6
address[6] => segment[0][17].RADDR6
address[6] => segment[0][16].WADDR6
address[6] => segment[0][16].RADDR6
address[6] => segment[0][15].WADDR6
address[6] => segment[0][15].RADDR6
address[6] => segment[0][14].WADDR6
address[6] => segment[0][14].RADDR6
address[6] => segment[0][13].WADDR6
address[6] => segment[0][13].RADDR6
address[6] => segment[0][12].WADDR6
address[6] => segment[0][12].RADDR6
address[6] => segment[0][11].WADDR6
address[6] => segment[0][11].RADDR6
address[6] => segment[0][10].WADDR6
address[6] => segment[0][10].RADDR6
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][31].WADDR7
address[7] => segment[0][31].RADDR7
address[7] => segment[0][30].WADDR7
address[7] => segment[0][30].RADDR7
address[7] => segment[0][29].WADDR7
address[7] => segment[0][29].RADDR7
address[7] => segment[0][28].WADDR7
address[7] => segment[0][28].RADDR7
address[7] => segment[0][27].WADDR7
address[7] => segment[0][27].RADDR7
address[7] => segment[0][26].WADDR7
address[7] => segment[0][26].RADDR7
address[7] => segment[0][25].WADDR7
address[7] => segment[0][25].RADDR7
address[7] => segment[0][24].WADDR7
address[7] => segment[0][24].RADDR7
address[7] => segment[0][23].WADDR7
address[7] => segment[0][23].RADDR7
address[7] => segment[0][22].WADDR7
address[7] => segment[0][22].RADDR7
address[7] => segment[0][21].WADDR7
address[7] => segment[0][21].RADDR7
address[7] => segment[0][20].WADDR7
address[7] => segment[0][20].RADDR7
address[7] => segment[0][19].WADDR7
address[7] => segment[0][19].RADDR7
address[7] => segment[0][18].WADDR7
address[7] => segment[0][18].RADDR7
address[7] => segment[0][17].WADDR7
address[7] => segment[0][17].RADDR7
address[7] => segment[0][16].WADDR7
address[7] => segment[0][16].RADDR7
address[7] => segment[0][15].WADDR7
address[7] => segment[0][15].RADDR7
address[7] => segment[0][14].WADDR7
address[7] => segment[0][14].RADDR7
address[7] => segment[0][13].WADDR7
address[7] => segment[0][13].RADDR7
address[7] => segment[0][12].WADDR7
address[7] => segment[0][12].RADDR7
address[7] => segment[0][11].WADDR7
address[7] => segment[0][11].RADDR7
address[7] => segment[0][10].WADDR7
address[7] => segment[0][10].RADDR7
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => ~NO_FANOUT~
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT
q[8] <= segment[0][8].DATAOUT
q[9] <= segment[0][9].DATAOUT
q[10] <= segment[0][10].DATAOUT
q[11] <= segment[0][11].DATAOUT
q[12] <= segment[0][12].DATAOUT
q[13] <= segment[0][13].DATAOUT
q[14] <= segment[0][14].DATAOUT
q[15] <= segment[0][15].DATAOUT
q[16] <= segment[0][16].DATAOUT
q[17] <= segment[0][17].DATAOUT
q[18] <= segment[0][18].DATAOUT
q[19] <= segment[0][19].DATAOUT
q[20] <= segment[0][20].DATAOUT
q[21] <= segment[0][21].DATAOUT
q[22] <= segment[0][22].DATAOUT
q[23] <= segment[0][23].DATAOUT
q[24] <= segment[0][24].DATAOUT
q[25] <= segment[0][25].DATAOUT
q[26] <= segment[0][26].DATAOUT
q[27] <= segment[0][27].DATAOUT
q[28] <= segment[0][28].DATAOUT
q[29] <= segment[0][29].DATAOUT
q[30] <= segment[0][30].DATAOUT
q[31] <= segment[0][31].DATAOUT


|CPU|C:inst9
clk => address[7].CLK
clk => address[6].CLK
clk => address[5].CLK
clk => address[4].CLK
clk => address[3].CLK
clk => address[2].CLK
clk => address[1].CLK
clk => address[0].CLK
clk => address_out[7]~reg0.CLK
clk => address_out[6]~reg0.CLK
clk => address_out[5]~reg0.CLK
clk => address_out[4]~reg0.CLK
clk => address_out[3]~reg0.CLK
clk => address_out[2]~reg0.CLK
clk => address_out[1]~reg0.CLK
clk => address_out[0]~reg0.CLK
C[0] => address~23.OUTPUTSELECT
C[0] => address~22.OUTPUTSELECT
C[0] => address~21.OUTPUTSELECT
C[0] => address~20.OUTPUTSELECT
C[0] => address~19.OUTPUTSELECT
C[0] => address~18.OUTPUTSELECT
C[0] => address~17.OUTPUTSELECT
C[0] => address~16.OUTPUTSELECT
C[1] => address~7.OUTPUTSELECT
C[1] => address~6.OUTPUTSELECT
C[1] => address~5.OUTPUTSELECT
C[1] => address~4.OUTPUTSELECT
C[1] => address~3.OUTPUTSELECT
C[1] => address~2.OUTPUTSELECT
C[1] => address~1.OUTPUTSELECT
C[1] => address~0.OUTPUTSELECT
C[2] => address~15.OUTPUTSELECT
C[2] => address~14.OUTPUTSELECT
C[2] => address~13.OUTPUTSELECT
C[2] => address~12.OUTPUTSELECT
C[2] => address~11.OUTPUTSELECT
C[2] => address~10.OUTPUTSELECT
C[2] => address~9.OUTPUTSELECT
C[2] => address~8.OUTPUTSELECT
C[3] => ~NO_FANOUT~
C[4] => ~NO_FANOUT~
C[5] => ~NO_FANOUT~
C[6] => ~NO_FANOUT~
C[7] => ~NO_FANOUT~
C[8] => ~NO_FANOUT~
C[9] => ~NO_FANOUT~
C[10] => ~NO_FANOUT~
C[11] => ~NO_FANOUT~
C[12] => ~NO_FANOUT~
C[13] => ~NO_FANOUT~
C[14] => ~NO_FANOUT~
C[15] => ~NO_FANOUT~
C[16] => ~NO_FANOUT~
C[17] => ~NO_FANOUT~
C[18] => ~NO_FANOUT~
C[19] => ~NO_FANOUT~
C[20] => ~NO_FANOUT~
C[21] => ~NO_FANOUT~
C[22] => ~NO_FANOUT~
C[23] => ~NO_FANOUT~
C[24] => ~NO_FANOUT~
C[25] => ~NO_FANOUT~
C[26] => ~NO_FANOUT~
C[27] => ~NO_FANOUT~
C[28] => ~NO_FANOUT~
C[29] => ~NO_FANOUT~
C[30] => ~NO_FANOUT~
C[31] => ~NO_FANOUT~
flag => Mux6.IN12
IR_in[0] => Mux7.IN20
IR_in[0] => Mux6.IN20
IR_in[0] => Mux5.IN20
IR_in[0] => Mux4.IN20
IR_in[0] => Mux3.IN20
IR_in[0] => Mux2.IN20
IR_in[0] => Mux1.IN20
IR_in[0] => Mux0.IN20
IR_in[1] => Mux7.IN19
IR_in[1] => Mux6.IN19
IR_in[1] => Mux5.IN19
IR_in[1] => Mux4.IN19
IR_in[1] => Mux3.IN19
IR_in[1] => Mux2.IN19
IR_in[1] => Mux1.IN19
IR_in[1] => Mux0.IN19
IR_in[2] => Mux7.IN18
IR_in[2] => Mux6.IN18
IR_in[2] => Mux5.IN18
IR_in[2] => Mux4.IN18
IR_in[2] => Mux3.IN18
IR_in[2] => Mux2.IN18
IR_in[2] => Mux1.IN18
IR_in[2] => Mux0.IN18
IR_in[3] => Mux7.IN17
IR_in[3] => Mux6.IN17
IR_in[3] => Mux5.IN17
IR_in[3] => Mux4.IN17
IR_in[3] => Mux3.IN17
IR_in[3] => Mux2.IN17
IR_in[3] => Mux1.IN17
IR_in[3] => Mux0.IN17
IR_in[4] => Mux7.IN16
IR_in[4] => Mux6.IN16
IR_in[4] => Mux5.IN16
IR_in[4] => Mux4.IN16
IR_in[4] => Mux3.IN16
IR_in[4] => Mux2.IN16
IR_in[4] => Mux1.IN16
IR_in[4] => Mux0.IN16
IR_in[5] => Mux7.IN15
IR_in[5] => Mux6.IN15
IR_in[5] => Mux5.IN15
IR_in[5] => Mux4.IN15
IR_in[5] => Mux3.IN15
IR_in[5] => Mux2.IN15
IR_in[5] => Mux1.IN15
IR_in[5] => Mux0.IN15
IR_in[6] => Mux7.IN14
IR_in[6] => Mux6.IN14
IR_in[6] => Mux5.IN14
IR_in[6] => Mux4.IN14
IR_in[6] => Mux3.IN14
IR_in[6] => Mux2.IN14
IR_in[6] => Mux1.IN14
IR_in[6] => Mux0.IN14
IR_in[7] => Mux7.IN13
IR_in[7] => Mux6.IN13
IR_in[7] => Mux5.IN13
IR_in[7] => Mux4.IN13
IR_in[7] => Mux3.IN13
IR_in[7] => Mux2.IN13
IR_in[7] => Mux1.IN13
IR_in[7] => Mux0.IN13
address_out[0] <= address_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[1] <= address_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[2] <= address_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[3] <= address_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[4] <= address_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[5] <= address_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[6] <= address_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[7] <= address_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|CPU|IR:inst2
clk => IR_out[7]~reg0.CLK
clk => IR_out[6]~reg0.CLK
clk => IR_out[5]~reg0.CLK
clk => IR_out[4]~reg0.CLK
clk => IR_out[3]~reg0.CLK
clk => IR_out[2]~reg0.CLK
clk => IR_out[1]~reg0.CLK
clk => IR_out[0]~reg0.CLK
IR_in[0] => IR_out[0]~reg0.DATAIN
IR_in[1] => IR_out[1]~reg0.DATAIN
IR_in[2] => IR_out[2]~reg0.DATAIN
IR_in[3] => IR_out[3]~reg0.DATAIN
IR_in[4] => IR_out[4]~reg0.DATAIN
IR_in[5] => IR_out[5]~reg0.DATAIN
IR_in[6] => IR_out[6]~reg0.DATAIN
IR_in[7] => IR_out[7]~reg0.DATAIN
IR_out[0] <= IR_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[1] <= IR_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[2] <= IR_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[3] <= IR_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[4] <= IR_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[5] <= IR_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[6] <= IR_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
IR_out[7] <= IR_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
C => IR_out[0]~reg0.ENA
C => IR_out[1]~reg0.ENA
C => IR_out[2]~reg0.ENA
C => IR_out[3]~reg0.ENA
C => IR_out[4]~reg0.ENA
C => IR_out[5]~reg0.ENA
C => IR_out[6]~reg0.ENA
C => IR_out[7]~reg0.ENA


|CPU|MBR:inst8
clk => MBR_out[15]~reg0.CLK
clk => MBR_out[14]~reg0.CLK
clk => MBR_out[13]~reg0.CLK
clk => MBR_out[12]~reg0.CLK
clk => MBR_out[11]~reg0.CLK
clk => MBR_out[10]~reg0.CLK
clk => MBR_out[9]~reg0.CLK
clk => MBR_out[8]~reg0.CLK
clk => MBR_out[7]~reg0.CLK
clk => MBR_out[6]~reg0.CLK
clk => MBR_out[5]~reg0.CLK
clk => MBR_out[4]~reg0.CLK
clk => MBR_out[3]~reg0.CLK
clk => MBR_out[2]~reg0.CLK
clk => MBR_out[1]~reg0.CLK
clk => MBR_out[0]~reg0.CLK
ACC_in[0] => MBR_out~31.DATAB
ACC_in[1] => MBR_out~30.DATAB
ACC_in[2] => MBR_out~29.DATAB
ACC_in[3] => MBR_out~28.DATAB
ACC_in[4] => MBR_out~27.DATAB
ACC_in[5] => MBR_out~26.DATAB
ACC_in[6] => MBR_out~25.DATAB
ACC_in[7] => MBR_out~24.DATAB
ACC_in[8] => MBR_out~23.DATAB
ACC_in[9] => MBR_out~22.DATAB
ACC_in[10] => MBR_out~21.DATAB
ACC_in[11] => MBR_out~20.DATAB
ACC_in[12] => MBR_out~19.DATAB
ACC_in[13] => MBR_out~18.DATAB
ACC_in[14] => MBR_out~17.DATAB
ACC_in[15] => MBR_out~16.DATAB
memory_in[0] => MBR_out~47.DATAB
memory_in[1] => MBR_out~46.DATAB
memory_in[2] => MBR_out~45.DATAB
memory_in[3] => MBR_out~44.DATAB
memory_in[4] => MBR_out~43.DATAB
memory_in[5] => MBR_out~42.DATAB
memory_in[6] => MBR_out~41.DATAB
memory_in[7] => MBR_out~40.DATAB
memory_in[8] => MBR_out~39.DATAB
memory_in[9] => MBR_out~38.DATAB
memory_in[10] => MBR_out~37.DATAB
memory_in[11] => MBR_out~36.DATAB
memory_in[12] => MBR_out~35.DATAB
memory_in[13] => MBR_out~34.DATAB
memory_in[14] => MBR_out~33.DATAB
memory_in[15] => MBR_out~32.DATAB
mul_in[0] => MBR_out~15.DATAB
mul_in[1] => MBR_out~14.DATAB
mul_in[2] => MBR_out~13.DATAB
mul_in[3] => MBR_out~12.DATAB
mul_in[4] => MBR_out~11.DATAB
mul_in[5] => MBR_out~10.DATAB
mul_in[6] => MBR_out~9.DATAB