we.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY we IS
  PORT (
         C : in  std_logic_vector(31 downto 0); 
          w : out std_logic
       );
  end we;
 
architecture behave of we is
   begin
     w<=C(23);
end behave;