ir.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IR is
port(
      clk: in std_logic;
      IR_in: in std_logic_vector(7 downto 0);
      IR_out: out std_logic_vector(7 downto 0);
	  C: in std_logic
);
end IR;
architecture IR_behave of IR is
begin
  process(clk)
   begin
    if clk'event and clk='1' then
      if C='1' then
       IR_out<=IR_in;
      end if;
   end if;
 end process;
end IR_behave;