br.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BR is
port(
   clk: in std_logic;
   BR_in: in std_logic_vector(15 downto 0);
   BR_out: out std_logic_vector(15 downto 0);
   C: in std_logic
);
end BR;
architecture BR_behave of BR is
  begin
   process(clk)
    begin
     if clk'event and clk='1' then
      if C='1' then
      BR_out<=BR_in;
      end if;
     end if;
   end process;
 end BR_behave;