change1.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY change IS
  PORT (
         MBR_in : in  std_logic_vector(15 downto 0); --MAR PC
         q     : out std_logic_vector(7 downto 0)
       );
  end change;
 
architecture behave of change is
   begin
     q(0)<=MBR_in(0);
     q(1)<=MBR_in(1);
     q(2)<=MBR_in(2);
     q(3)<=MBR_in(3);
     q(4)<=MBR_in(4);
     q(5)<=MBR_in(5);
     q(6)<=MBR_in(6);
     q(7)<=MBR_in(7);
end behave;