📄 ram.sim.rpt
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; |RAM|q[0] ; |RAM|q[0] ; padio ;
+----------------------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+----------------------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][15] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][14] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[14] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][13] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[13] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][12] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[12] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][11] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[11] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][10] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[10] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][9] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[9] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][8] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[8] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][7] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][6] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][5] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][4] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[4] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][3] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[3] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][2] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[2] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][0] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[0] ; dataout ;
; |RAM|data[15] ; |RAM|data[15]~corein ; dataout ;
; |RAM|we ; |RAM|we~corein ; dataout ;
; |RAM|address[2] ; |RAM|address[2]~corein ; dataout ;
; |RAM|address[3] ; |RAM|address[3]~corein ; dataout ;
; |RAM|address[6] ; |RAM|address[6]~corein ; dataout ;
; |RAM|address[7] ; |RAM|address[7]~corein ; dataout ;
; |RAM|data[14] ; |RAM|data[14]~corein ; dataout ;
; |RAM|data[13] ; |RAM|data[13]~corein ; dataout ;
; |RAM|data[12] ; |RAM|data[12]~corein ; dataout ;
; |RAM|data[11] ; |RAM|data[11]~corein ; dataout ;
; |RAM|data[10] ; |RAM|data[10]~corein ; dataout ;
; |RAM|data[9] ; |RAM|data[9]~corein ; dataout ;
; |RAM|data[8] ; |RAM|data[8]~corein ; dataout ;
; |RAM|data[7] ; |RAM|data[7]~corein ; dataout ;
; |RAM|data[6] ; |RAM|data[6]~corein ; dataout ;
; |RAM|data[5] ; |RAM|data[5]~corein ; dataout ;
; |RAM|data[4] ; |RAM|data[4]~corein ; dataout ;
; |RAM|data[3] ; |RAM|data[3]~corein ; dataout ;
; |RAM|data[2] ; |RAM|data[2]~corein ; dataout ;
; |RAM|data[1] ; |RAM|data[1]~corein ; dataout ;
; |RAM|data[0] ; |RAM|data[0]~corein ; dataout ;
; |RAM|q[15] ; |RAM|q[15] ; padio ;
; |RAM|q[14] ; |RAM|q[14] ; padio ;
; |RAM|q[13] ; |RAM|q[13] ; padio ;
; |RAM|q[12] ; |RAM|q[12] ; padio ;
; |RAM|q[11] ; |RAM|q[11] ; padio ;
; |RAM|q[10] ; |RAM|q[10] ; padio ;
; |RAM|q[9] ; |RAM|q[9] ; padio ;
; |RAM|q[8] ; |RAM|q[8] ; padio ;
; |RAM|q[7] ; |RAM|q[7] ; padio ;
; |RAM|q[6] ; |RAM|q[6] ; padio ;
; |RAM|q[5] ; |RAM|q[5] ; padio ;
; |RAM|q[4] ; |RAM|q[4] ; padio ;
; |RAM|q[3] ; |RAM|q[3] ; padio ;
; |RAM|q[2] ; |RAM|q[2] ; padio ;
; |RAM|q[0] ; |RAM|q[0] ; padio ;
+----------------------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Mon Apr 21 11:08:52 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off RAM -c RAM
Info: Using vector source file "D:/RAM/RAM.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 12.07 %
Info: Number of transitions in simulation is 211
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 92 megabytes of memory during processing
Info: Processing ended: Mon Apr 21 11:08:53 2008
Info: Elapsed time: 00:00:01
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