📄 ram.sim.rpt
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; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|content ;
+---------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 12.07 % ;
; Total nodes checked ; 58 ;
; Total output ports checked ; 58 ;
; Total output ports with complete 1/0-value coverage ; 7 ;
; Total output ports with no 1/0-value coverage ; 51 ;
; Total output ports with no 1-value coverage ; 51 ;
; Total output ports with no 0-value coverage ; 51 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+---------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][1] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[1] ; dataout ;
; |RAM|inclock ; |RAM|inclock~corein ; dataout ;
; |RAM|address[0] ; |RAM|address[0]~corein ; dataout ;
; |RAM|address[1] ; |RAM|address[1]~corein ; dataout ;
; |RAM|address[4] ; |RAM|address[4]~corein ; dataout ;
; |RAM|address[5] ; |RAM|address[5]~corein ; dataout ;
; |RAM|q[1] ; |RAM|q[1] ; padio ;
+---------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+----------------------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------------+-------------------------------------------------------------------------+------------------+
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][15] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[15] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][14] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[14] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][13] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[13] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][12] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[12] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][11] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[11] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][10] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[10] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][9] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[9] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][8] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[8] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][7] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[7] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][6] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[6] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][5] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[5] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][4] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[4] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][3] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[3] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][2] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[2] ; dataout ;
; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|segment[0][0] ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|q[0] ; dataout ;
; |RAM|data[15] ; |RAM|data[15]~corein ; dataout ;
; |RAM|we ; |RAM|we~corein ; dataout ;
; |RAM|address[2] ; |RAM|address[2]~corein ; dataout ;
; |RAM|address[3] ; |RAM|address[3]~corein ; dataout ;
; |RAM|address[6] ; |RAM|address[6]~corein ; dataout ;
; |RAM|address[7] ; |RAM|address[7]~corein ; dataout ;
; |RAM|data[14] ; |RAM|data[14]~corein ; dataout ;
; |RAM|data[13] ; |RAM|data[13]~corein ; dataout ;
; |RAM|data[12] ; |RAM|data[12]~corein ; dataout ;
; |RAM|data[11] ; |RAM|data[11]~corein ; dataout ;
; |RAM|data[10] ; |RAM|data[10]~corein ; dataout ;
; |RAM|data[9] ; |RAM|data[9]~corein ; dataout ;
; |RAM|data[8] ; |RAM|data[8]~corein ; dataout ;
; |RAM|data[7] ; |RAM|data[7]~corein ; dataout ;
; |RAM|data[6] ; |RAM|data[6]~corein ; dataout ;
; |RAM|data[5] ; |RAM|data[5]~corein ; dataout ;
; |RAM|data[4] ; |RAM|data[4]~corein ; dataout ;
; |RAM|data[3] ; |RAM|data[3]~corein ; dataout ;
; |RAM|data[2] ; |RAM|data[2]~corein ; dataout ;
; |RAM|data[1] ; |RAM|data[1]~corein ; dataout ;
; |RAM|data[0] ; |RAM|data[0]~corein ; dataout ;
; |RAM|q[15] ; |RAM|q[15] ; padio ;
; |RAM|q[14] ; |RAM|q[14] ; padio ;
; |RAM|q[13] ; |RAM|q[13] ; padio ;
; |RAM|q[12] ; |RAM|q[12] ; padio ;
; |RAM|q[11] ; |RAM|q[11] ; padio ;
; |RAM|q[10] ; |RAM|q[10] ; padio ;
; |RAM|q[9] ; |RAM|q[9] ; padio ;
; |RAM|q[8] ; |RAM|q[8] ; padio ;
; |RAM|q[7] ; |RAM|q[7] ; padio ;
; |RAM|q[6] ; |RAM|q[6] ; padio ;
; |RAM|q[5] ; |RAM|q[5] ; padio ;
; |RAM|q[4] ; |RAM|q[4] ; padio ;
; |RAM|q[3] ; |RAM|q[3] ; padio ;
; |RAM|q[2] ; |RAM|q[2] ; padio ;
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