📄 mbr.rpt
字号:
-- Node name is ':70'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !cs15 & _LC5_B11
# cs15 & memory_in13;
-- Node name is ':72'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !cs15 & _LC4_B11
# cs15 & memory_in12;
-- Node name is ':74'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !cs15 & _LC2_B11
# cs15 & memory_in11;
-- Node name is ':76'
-- Equation name is '_LC5_C21', type is buried
_LC5_C21 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !cs15 & _LC6_C21
# cs15 & memory_in10;
-- Node name is ':78'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !cs15 & _LC4_C21
# cs15 & memory_in9;
-- Node name is ':80'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !cs15 & _LC2_C21
# cs15 & memory_in8;
-- Node name is ':82'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !cs15 & _LC7_A15
# cs15 & memory_in7;
-- Node name is ':84'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !cs15 & _LC6_A15
# cs15 & memory_in6;
-- Node name is ':86'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !cs15 & _LC4_A15
# cs15 & memory_in5;
-- Node name is ':88'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !cs15 & _LC2_A15
# cs15 & memory_in4;
-- Node name is ':90'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !cs15 & _LC7_B24
# cs15 & memory_in3;
-- Node name is ':92'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = !cs15 & _LC5_B24
# cs15 & memory_in2;
-- Node name is ':94'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !cs15 & _LC4_B24
# cs15 & memory_in1;
-- Node name is ':96'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = !cs15 & _LC3_B24
# cs15 & memory_in0;
-- Node name is ':401'
-- Equation name is '_LC8_C21', type is buried
_LC8_C21 = LCELL( _EQ017);
_EQ017 = acc_in15 & cs16
# !cs16 & _LC3_C21;
-- Node name is ':413'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ018);
_EQ018 = acc_in14 & cs16
# !cs16 & _LC3_B11;
-- Node name is ':422'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ019);
_EQ019 = acc_in13 & cs16
# !cs16 & _LC1_B11;
-- Node name is ':431'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ020);
_EQ020 = acc_in12 & cs16
# !cs16 & _LC8_B11;
-- Node name is ':440'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ021);
_EQ021 = acc_in11 & cs16
# !cs16 & _LC6_B11;
-- Node name is ':449'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ022);
_EQ022 = acc_in10 & cs16
# !cs16 & _LC5_C21;
-- Node name is ':458'
-- Equation name is '_LC4_C21', type is buried
_LC4_C21 = LCELL( _EQ023);
_EQ023 = acc_in9 & cs16
# !cs16 & _LC1_C21;
-- Node name is ':467'
-- Equation name is '_LC2_C21', type is buried
_LC2_C21 = LCELL( _EQ024);
_EQ024 = acc_in8 & cs16
# !cs16 & _LC7_C21;
-- Node name is ':476'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = LCELL( _EQ025);
_EQ025 = acc_in7 & cs16
# !cs16 & _LC5_A15;
-- Node name is ':485'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ026);
_EQ026 = acc_in6 & cs16
# !cs16 & _LC3_A15;
-- Node name is ':494'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ027);
_EQ027 = acc_in5 & cs16
# !cs16 & _LC1_A15;
-- Node name is ':503'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ028);
_EQ028 = acc_in4 & cs16
# !cs16 & _LC8_A15;
-- Node name is ':512'
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = LCELL( _EQ029);
_EQ029 = acc_in3 & cs16
# !cs16 & _LC2_B24;
-- Node name is ':521'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ030);
_EQ030 = acc_in2 & cs16
# !cs16 & _LC8_B24;
-- Node name is ':530'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = LCELL( _EQ031);
_EQ031 = acc_in1 & cs16
# !cs16 & _LC1_B24;
-- Node name is ':539'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ032);
_EQ032 = acc_in0 & cs16
# !cs16 & _LC6_B24;
Project Information q:\information\cpu2\mbr.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,949K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -