📄 mbr.rpt
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Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: q:\information\cpu2\mbr.rpt
mbr
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - 23 OUTPUT 0 1 0 0 mbr_out0
22 - - B -- OUTPUT 0 1 0 0 mbr_out1
65 - - B -- OUTPUT 0 1 0 0 mbr_out2
78 - - - 24 OUTPUT 0 1 0 0 mbr_out3
69 - - A -- OUTPUT 0 1 0 0 mbr_out4
73 - - A -- OUTPUT 0 1 0 0 mbr_out5
48 - - - 15 OUTPUT 0 1 0 0 mbr_out6
70 - - A -- OUTPUT 0 1 0 0 mbr_out7
58 - - C -- OUTPUT 0 1 0 0 mbr_out8
62 - - C -- OUTPUT 0 1 0 0 mbr_out9
59 - - C -- OUTPUT 0 1 0 0 mbr_out10
24 - - B -- OUTPUT 0 1 0 0 mbr_out11
25 - - B -- OUTPUT 0 1 0 0 mbr_out12
21 - - B -- OUTPUT 0 1 0 0 mbr_out13
3 - - - 12 OUTPUT 0 1 0 0 mbr_out14
61 - - C -- OUTPUT 0 1 0 0 mbr_out15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: q:\information\cpu2\mbr.rpt
mbr
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 21 DFFE + 2 1 1 1 :66
- 3 - B 11 DFFE + 2 1 1 1 :68
- 1 - B 11 DFFE + 2 1 1 1 :70
- 8 - B 11 DFFE + 2 1 1 1 :72
- 6 - B 11 DFFE + 2 1 1 1 :74
- 5 - C 21 DFFE + 2 1 1 1 :76
- 1 - C 21 DFFE + 2 1 1 1 :78
- 7 - C 21 DFFE + 2 1 1 1 :80
- 5 - A 15 DFFE + 2 1 1 1 :82
- 3 - A 15 DFFE + 2 1 1 1 :84
- 1 - A 15 DFFE + 2 1 1 1 :86
- 8 - A 15 DFFE + 2 1 1 1 :88
- 2 - B 24 DFFE + 2 1 1 1 :90
- 8 - B 24 DFFE + 2 1 1 1 :92
- 1 - B 24 DFFE + 2 1 1 1 :94
- 6 - B 24 DFFE + 2 1 1 1 :96
- 8 - C 21 OR2 2 1 0 1 :401
- 7 - B 11 OR2 2 1 0 1 :413
- 5 - B 11 OR2 2 1 0 1 :422
- 4 - B 11 OR2 2 1 0 1 :431
- 2 - B 11 OR2 2 1 0 1 :440
- 6 - C 21 OR2 2 1 0 1 :449
- 4 - C 21 OR2 2 1 0 1 :458
- 2 - C 21 OR2 2 1 0 1 :467
- 7 - A 15 OR2 2 1 0 1 :476
- 6 - A 15 OR2 2 1 0 1 :485
- 4 - A 15 OR2 2 1 0 1 :494
- 2 - A 15 OR2 2 1 0 1 :503
- 7 - B 24 OR2 2 1 0 1 :512
- 5 - B 24 OR2 2 1 0 1 :521
- 4 - B 24 OR2 2 1 0 1 :530
- 3 - B 24 OR2 2 1 0 1 :539
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: q:\information\cpu2\mbr.rpt
mbr
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 4/ 48( 8%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 6/ 96( 6%) 8/ 48( 16%) 4/ 48( 8%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 6/ 48( 12%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: q:\information\cpu2\mbr.rpt
mbr
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: q:\information\cpu2\mbr.rpt
mbr
** EQUATIONS **
acc_in0 : INPUT;
acc_in1 : INPUT;
acc_in2 : INPUT;
acc_in3 : INPUT;
acc_in4 : INPUT;
acc_in5 : INPUT;
acc_in6 : INPUT;
acc_in7 : INPUT;
acc_in8 : INPUT;
acc_in9 : INPUT;
acc_in10 : INPUT;
acc_in11 : INPUT;
acc_in12 : INPUT;
acc_in13 : INPUT;
acc_in14 : INPUT;
acc_in15 : INPUT;
clk : INPUT;
cs15 : INPUT;
cs16 : INPUT;
memory_in0 : INPUT;
memory_in1 : INPUT;
memory_in2 : INPUT;
memory_in3 : INPUT;
memory_in4 : INPUT;
memory_in5 : INPUT;
memory_in6 : INPUT;
memory_in7 : INPUT;
memory_in8 : INPUT;
memory_in9 : INPUT;
memory_in10 : INPUT;
memory_in11 : INPUT;
memory_in12 : INPUT;
memory_in13 : INPUT;
memory_in14 : INPUT;
memory_in15 : INPUT;
-- Node name is 'mbr_out0'
-- Equation name is 'mbr_out0', type is output
mbr_out0 = _LC6_B24;
-- Node name is 'mbr_out1'
-- Equation name is 'mbr_out1', type is output
mbr_out1 = _LC1_B24;
-- Node name is 'mbr_out2'
-- Equation name is 'mbr_out2', type is output
mbr_out2 = _LC8_B24;
-- Node name is 'mbr_out3'
-- Equation name is 'mbr_out3', type is output
mbr_out3 = _LC2_B24;
-- Node name is 'mbr_out4'
-- Equation name is 'mbr_out4', type is output
mbr_out4 = _LC8_A15;
-- Node name is 'mbr_out5'
-- Equation name is 'mbr_out5', type is output
mbr_out5 = _LC1_A15;
-- Node name is 'mbr_out6'
-- Equation name is 'mbr_out6', type is output
mbr_out6 = _LC3_A15;
-- Node name is 'mbr_out7'
-- Equation name is 'mbr_out7', type is output
mbr_out7 = _LC5_A15;
-- Node name is 'mbr_out8'
-- Equation name is 'mbr_out8', type is output
mbr_out8 = _LC7_C21;
-- Node name is 'mbr_out9'
-- Equation name is 'mbr_out9', type is output
mbr_out9 = _LC1_C21;
-- Node name is 'mbr_out10'
-- Equation name is 'mbr_out10', type is output
mbr_out10 = _LC5_C21;
-- Node name is 'mbr_out11'
-- Equation name is 'mbr_out11', type is output
mbr_out11 = _LC6_B11;
-- Node name is 'mbr_out12'
-- Equation name is 'mbr_out12', type is output
mbr_out12 = _LC8_B11;
-- Node name is 'mbr_out13'
-- Equation name is 'mbr_out13', type is output
mbr_out13 = _LC1_B11;
-- Node name is 'mbr_out14'
-- Equation name is 'mbr_out14', type is output
mbr_out14 = _LC3_B11;
-- Node name is 'mbr_out15'
-- Equation name is 'mbr_out15', type is output
mbr_out15 = _LC3_C21;
-- Node name is ':66'
-- Equation name is '_LC3_C21', type is buried
_LC3_C21 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cs15 & _LC8_C21
# cs15 & memory_in15;
-- Node name is ':68'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !cs15 & _LC7_B11
# cs15 & memory_in14;
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