mar.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY MAR IS
	PORT
	(	pc,mbr		:  IN	std_logic_vector(7 downto 0);
		cs          :  IN   std_logic_vector(31 downto 0); 
        clk	        :  IN   std_logic;
		mar_out		    :  out  std_logic_vector(7 downto 0)
    );
END MAR;

ARCHITECTURE behave OF MAR IS
BEGIN
	PROCESS(clk)
		BEGIN
			IF clk'event and clk='1' THEN
				if cs(12)='1' then
					mar_out<=pc;
				elsif cs(13)='1' then
					mar_out<=mbr; 
				end if;
			END IF;
	END PROCESS;
END behave;