behind.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY behind IS
  PORT (
         mbr_in : in  std_logic_vector(15 downto 0); --IR
         q      : out std_logic_vector(7 downto 0)
       );
  end behind;
 
architecture behave of behind is
   begin
     q(0)<=mbr_in(8);
     q(1)<=mbr_in(9);
     q(2)<=mbr_in(10);
     q(3)<=mbr_in(11);
     q(4)<=mbr_in(12);
     q(5)<=mbr_in(13);
     q(6)<=mbr_in(14);
     q(7)<=mbr_in(15);
end behave;