pc.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY PC IS
	PORT
	(	mbr_in	:  IN  std_logic_vector(7 downto 0);  --MBR[15..8]
        cs      :  IN  std_logic_vector(31 downto 0);
		clk     :  IN  std_logic;
        pc_out  :  OUT std_logic_vector(7 downto 0)
    );
END PC;

ARCHITECTURE behave OF PC IS
  BEGIN
	PROCESS(clk)
        variable temp:std_logic_vector(7 downto 0);
		BEGIN
			if clk'event and clk='1' then
			   if cs(20)='1' THEN   --reset
				  temp:="00000000";
			   elsif cs(18)='1' then  --MBR to PC
					temp:=mbr_in;
			   elsif cs(19)='1' then  --increment
					temp:=temp+1;
			   end if;
            pc_out<=temp;
			END IF;       
	END PROCESS;
END behave;