📄 control_unit.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY control_unit IS
PORT
( clk : in std_logic;
flag : in std_logic; --ACC is 0 or not
cs : in std_logic_vector(31 downto 0);
IR_out : in std_logic_vector(7 downto 0);
address_out : out std_logic_vector(7 downto 0)
);
END control_unit ;
ARCHITECTURE behave OF control_unit IS
BEGIN
PROCESS (clk)
variable address : std_logic_vector(7 downto 0);
BEGIN
IF clk'event and clk = '1' THEN
if cs(4)='1' then --Increament car
address:=address+1;
elsif cs(5)='1' then --reset car
address:="00000000";
elsif cs(6)='1' then --load
case IR_out is
when "00000001"=> --store
address:="00010000";
when "00000010"=> --load
address:="00010100";
when "00000011"=> --add
address:="00011001";
when "00000100"=> --sub
address:="00011110";
when "00001010"=> --and
address:="00000110";
when "00001011"=> --or
address:="00001000";
when "00001100"=> --not
address:="00111001";
when "00001101"=> --shiftr
address:="00111110";
when "00001110"=> --shilfl
address:="01000100";
when "00001000"=> --mpy
address:="00101001";
when "00000101"=> --jmpegz
if flag='0' then
address:="00100011";
else address:="00100101";
end if;
when "00000111"=> --halt
address:="00100111";
when others=>null;
end case;
end if;
address_out<=address;
END IF;
END PROCESS;
END behave;
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