ir.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY IR IS
	PORT
	(	mbr_in  : IN  std_logic_vector(7 downto 0); --MBR[15..8]
		cs      : in  std_logic_vector(31 downto 0);
        clk	    : IN  std_logic;
		ir_out  : out std_logic_vector(7 downto 0)
    );
END IR;

ARCHITECTURE behave OF IR IS
BEGIN
	PROCESS(clk)
		BEGIN
			IF clk'event and clk='1' THEN
				if cs(17)='1' then
					ir_out<=mbr_in;
				end if;
			END IF;
	END PROCESS;
END behave;