control_unit.rpt

实现简单CPU功能的源码

-- Node name is ':807' 
-- Equation name is '_LC2_B24', type is buried 
_LC2_B24 = LCELL( _EQ049);
  _EQ049 =  _LC2_B22 & !_LC6_B20
         #  _LC5_B23 & !_LC6_B20
         #  _LC7_B20;

-- Node name is ':819' 
-- Equation name is '_LC3_B17', type is buried 
_LC3_B17 = LCELL( _EQ050);
  _EQ050 =  address1 & !_LC2_B20
         # !_LC2_B20 &  _LC8_B20
         # !flag &  _LC2_B20;

-- Node name is ':828' 
-- Equation name is '_LC5_B17', type is buried 
_LC5_B17 = LCELL( _EQ051);
  _EQ051 =  _LC8_B22
         # !_LC1_B20 & !_LC1_B22 &  _LC3_B17;

-- Node name is '~839~1' 
-- Equation name is '~839~1', location is LC2_B16, type is buried.
-- synthesized logic cell 
_LC2_B16 = LCELL( _EQ052);
  _EQ052 = !_LC3_B20 & !_LC3_B23;

-- Node name is '~840~1' 
-- Equation name is '~840~1', location is LC5_B23, type is buried.
-- synthesized logic cell 
_LC5_B23 = LCELL( _EQ053);
  _EQ053 =  _LC4_B20
         # !IR_out3 & !_LC6_B23 & !_LC7_B23;

-- Node name is '~861~1' 
-- Equation name is '~861~1', location is LC4_B17, type is buried.
-- synthesized logic cell 
!_LC4_B17 = _LC4_B17~NOT;
_LC4_B17~NOT = LCELL( _EQ054);
  _EQ054 = !_LC1_B22 & !_LC2_B20 & !_LC8_B20;

-- Node name is '~861~2' 
-- Equation name is '~861~2', location is LC1_B18, type is buried.
-- synthesized logic cell 
!_LC1_B18 = _LC1_B18~NOT;
_LC1_B18~NOT = LCELL( _EQ055);
  _EQ055 = !_LC2_B20 & !_LC8_B20;

-- Node name is ':870' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ056);
  _EQ056 =  address0 &  _LC7_B22
         #  _LC4_B17 &  _LC7_B22
         #  _LC3_B23;

-- Node name is ':882' 
-- Equation name is '_LC1_B16', type is buried 
_LC1_B16 = LCELL( _EQ057);
  _EQ057 = !_LC3_B20 & !_LC5_B23 &  _LC8_B16
         #  _LC6_B20;

-- Node name is '~900~1' 
-- Equation name is '~900~1', location is LC7_B22, type is buried.
-- synthesized logic cell 
!_LC7_B22 = _LC7_B22~NOT;
_LC7_B22~NOT = LCELL( _EQ058);
  _EQ058 =  _LC8_B22
         #  _LC1_B20;

-- Node name is '~900~2' 
-- Equation name is '~900~2', location is LC3_B19, type is buried.
-- synthesized logic cell 
_LC3_B19 = LCELL( _EQ059);
  _EQ059 =  _LC2_B19 & !_LC3_B20 & !_LC3_B23 & !_LC5_B23;

-- Node name is '~900~3' 
-- Equation name is '~900~3', location is LC4_B19, type is buried.
-- synthesized logic cell 
_LC4_B19 = LCELL( _EQ060);
  _EQ060 =  _LC3_B19 & !_LC4_B17 & !_LC5_B20 &  _LC7_B22;

-- Node name is ':914' 
-- Equation name is '_LC5_B19', type is buried 
_LC5_B19 = LCELL( _EQ061);
  _EQ061 =  address7 &  _LC2_B15 &  _LC4_B19
         #  address7 & !cs6 &  _LC2_B15;

-- Node name is ':918' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ062);
  _EQ062 =  _LC6_B16 &  _LC7_B16
         #  address6 & !cs6;

-- Node name is '~919~1' 
-- Equation name is '~919~1', location is LC1_B24, type is buried.
-- synthesized logic cell 
_LC1_B24 = LCELL( _EQ063);
  _EQ063 =  cs6 & !_LC5_B20 & !_LC6_B20 & !_LC7_B20;

-- Node name is '~919~2' 
-- Equation name is '~919~2', location is LC6_B16, type is buried.
-- synthesized logic cell 
_LC6_B16 = LCELL( _EQ064);
  _EQ064 =  _LC1_B24 &  _LC2_B16 & !_LC5_B23 & !_LC8_B22;

-- Node name is ':930' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ065);
  _EQ065 =  _LC5_B13 &  _LC5_B16
         #  address5 & !cs6;

-- Node name is '~931~1' 
-- Equation name is '~931~1', location is LC5_B16, type is buried.
-- synthesized logic cell 
_LC5_B16 = LCELL( _EQ066);
  _EQ066 =  _LC1_B24 & !_LC3_B20 & !_LC5_B23;

-- Node name is '~931~2' 
-- Equation name is '~931~2', location is LC2_B19, type is buried.
-- synthesized logic cell 
_LC2_B19 = LCELL( _EQ067);
  _EQ067 = !_LC6_B20 & !_LC7_B20;

-- Node name is ':950' 
-- Equation name is '_LC7_B13', type is buried 
_LC7_B13 = LCELL( _EQ068);
  _EQ068 =  cs6 &  _LC2_B15 &  _LC6_B13
         #  address4 & !cs6 &  _LC2_B15;

-- Node name is ':955' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ069);
  _EQ069 =  cs6 &  _LC4_B23 &  _LC6_B24
         #  cs6 &  _LC3_B18 &  _LC6_B24;

-- Node name is ':962' 
-- Equation name is '_LC7_B18', type is buried 
_LC7_B18 = LCELL( _EQ070);
  _EQ070 =  _LC2_B15 &  _LC5_B18
         #  address3 & !cs6 &  _LC2_B15;

-- Node name is ':966' 
-- Equation name is '_LC3_B24', type is buried 
_LC3_B24 = LCELL( _EQ071);
  _EQ071 =  cs6 &  _LC2_B24 & !_LC5_B20
         #  address2 & !cs6;

-- Node name is '~979~1' 
-- Equation name is '~979~1', location is LC1_B21, type is buried.
-- synthesized logic cell 
_LC1_B21 = LCELL( _EQ072);
  _EQ072 =  cs6 & !_LC6_B20 &  _LC6_B24;

-- Node name is ':979' 
-- Equation name is '_LC7_B17', type is buried 
_LC7_B17 = LCELL( _EQ073);
  _EQ073 =  _LC1_B21 &  _LC5_B23
         #  _LC1_B21 &  _LC2_B16 &  _LC5_B17;

-- Node name is '~986~1' 
-- Equation name is '~986~1', location is LC2_B15, type is buried.
-- synthesized logic cell 
_LC2_B15 = LCELL( _EQ074);
  _EQ074 = !cs4 & !cs5;

-- Node name is ':986' 
-- Equation name is '_LC8_B17', type is buried 
_LC8_B17 = LCELL( _EQ075);
  _EQ075 =  _LC2_B15 &  _LC7_B17
         #  address1 & !cs6 &  _LC2_B15;

-- Node name is ':990' 
-- Equation name is '_LC8_B15', type is buried 
_LC8_B15 = LCELL( _EQ076);
  _EQ076 =  cs6 &  _LC1_B16 &  _LC6_B24
         #  address0 & !cs6;

-- Node name is '~991~1' 
-- Equation name is '~991~1', location is LC6_B24, type is buried.
-- synthesized logic cell 
_LC6_B24 = LCELL( _EQ077);
  _EQ077 = !_LC5_B20 & !_LC7_B20;



Project Information                       q:\information\cpu2\control_unit.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 17,280K