📄 control_unit.rpt
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Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: q:\information\cpu2\control_unit.rpt
control_unit
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
49 - - - 16 OUTPUT 0 1 0 0 address_out0
50 - - - 17 OUTPUT 0 1 0 0 address_out1
80 - - - 23 OUTPUT 0 1 0 0 address_out2
51 - - - 18 OUTPUT 0 1 0 0 address_out3
66 - - B -- OUTPUT 0 1 0 0 address_out4
48 - - - 15 OUTPUT 0 1 0 0 address_out5
65 - - B -- OUTPUT 0 1 0 0 address_out6
67 - - B -- OUTPUT 0 1 0 0 address_out7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: q:\information\cpu2\control_unit.rpt
control_unit
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - B 24 AND2 0 3 0 3 |LPM_ADD_SUB:284|addcore:adder|:125
- 6 - B 18 AND2 0 2 0 5 |LPM_ADD_SUB:284|addcore:adder|:129
- 6 - B 19 AND2 0 4 0 2 |LPM_ADD_SUB:284|addcore:adder|:141
- 4 - B 24 OR2 0 3 0 2 |LPM_ADD_SUB:284|addcore:adder|:150
- 4 - B 13 OR2 0 3 0 2 |LPM_ADD_SUB:284|addcore:adder|:153
- 8 - B 19 OR2 0 4 0 2 |LPM_ADD_SUB:284|addcore:adder|:154
- 1 - B 19 DFFE + 1 3 1 0 :43
- 5 - B 15 DFFE + 2 2 1 0 :45
- 3 - B 15 DFFE + 2 2 1 0 :47
- 3 - B 13 DFFE + 1 3 1 0 :49
- 4 - B 18 DFFE + 1 3 1 0 :51
- 5 - B 24 DFFE + 2 2 1 0 :53
- 1 - B 17 DFFE + 1 3 1 0 :55
- 6 - B 15 DFFE + 2 2 1 0 :57
- 7 - B 19 DFFE + 1 2 0 2 address7 (:59)
- 7 - B 15 DFFE + 1 3 0 4 address6 (:60)
- 1 - B 15 DFFE + 1 3 0 5 address5 (:61)
- 8 - B 13 DFFE + 1 2 0 6 address4 (:62)
- 8 - B 18 DFFE + 1 2 0 4 address3 (:63)
- 7 - B 24 DFFE + 1 3 0 4 address2 (:64)
- 6 - B 17 DFFE + 1 2 0 5 address1 (:65)
- 4 - B 15 DFFE + 2 1 0 7 address0 (:66)
- 8 - B 20 AND2 3 1 0 4 :392
- 2 - B 20 AND2 3 1 0 4 :412
- 1 - B 22 OR2 ! 3 1 0 4 :432
- 1 - B 20 OR2 ! 3 1 0 6 :452
- 8 - B 22 AND2 3 1 0 5 :472
- 3 - B 23 OR2 ! 0 2 0 4 :492
- 3 - B 20 OR2 ! 3 1 0 5 :512
- 2 - B 23 OR2 s 1 1 0 6 ~532~1
- 4 - B 20 AND2 3 1 0 3 :532
- 7 - B 23 OR2 s 3 0 0 3 ~552~1
- 6 - B 23 OR2 s 4 0 0 4 ~572~1
- 1 - B 23 OR2 s 1 1 0 5 ~572~2
- 6 - B 20 OR2 ! 3 1 0 6 :572
- 7 - B 20 OR2 ! 3 1 0 4 :592
- 5 - B 20 OR2 ! 3 1 0 4 :612
- 7 - B 16 OR2 0 3 0 1 :630
- 3 - B 22 OR2 s 0 2 0 2 ~675~1
- 5 - B 13 OR2 0 4 0 1 :675
- 1 - B 13 AND2 0 3 0 1 :713
- 2 - B 13 OR2 0 4 0 1 :725
- 4 - B 23 OR2 s 1 3 0 2 ~732~1
- 6 - B 13 OR2 0 3 0 1 :732
- 2 - B 18 OR2 0 4 0 1 :752
- 3 - B 18 OR2 0 4 0 1 :764
- 2 - B 17 OR2 1 3 0 1 :780
- 2 - B 22 OR2 0 4 0 1 :800
- 2 - B 24 OR2 0 4 0 1 :807
- 3 - B 17 OR2 1 3 0 1 :819
- 5 - B 17 OR2 0 4 0 1 :828
- 2 - B 16 AND2 s 0 2 0 4 ~839~1
- 5 - B 23 OR2 s 1 3 0 6 ~840~1
- 4 - B 17 AND2 s ! 0 3 0 5 ~861~1
- 1 - B 18 AND2 s ! 0 2 0 1 ~861~2
- 8 - B 16 OR2 0 4 0 1 :870
- 1 - B 16 OR2 0 4 0 1 :882
- 7 - B 22 OR2 s ! 0 2 0 3 ~900~1
- 3 - B 19 AND2 s 0 4 0 1 ~900~2
- 4 - B 19 AND2 s 0 4 0 1 ~900~3
- 5 - B 19 OR2 1 3 0 2 :914
- 4 - B 16 OR2 1 3 0 2 :918
- 1 - B 24 AND2 s 1 3 0 2 ~919~1
- 6 - B 16 AND2 s 0 4 0 1 ~919~2
- 3 - B 16 OR2 1 3 0 2 :930
- 5 - B 16 AND2 s 0 3 0 1 ~931~1
- 2 - B 19 AND2 s 0 2 0 1 ~931~2
- 7 - B 13 OR2 1 3 0 2 :950
- 5 - B 18 OR2 1 3 0 1 :955
- 7 - B 18 OR2 1 3 0 2 :962
- 3 - B 24 OR2 1 3 0 2 :966
- 1 - B 21 AND2 s 1 2 0 1 ~979~1
- 7 - B 17 OR2 0 4 0 1 :979
- 2 - B 15 AND2 s 2 0 0 7 ~986~1
- 8 - B 17 OR2 1 3 0 2 :986
- 8 - B 15 OR2 1 3 0 2 :990
- 6 - B 24 AND2 s 0 2 0 4 ~991~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: q:\information\cpu2\control_unit.rpt
control_unit
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 20/ 96( 20%) 0/ 48( 0%) 30/ 48( 62%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: q:\information\cpu2\control_unit.rpt
control_unit
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 clk
Device-Specific Information: q:\information\cpu2\control_unit.rpt
control_unit
** EQUATIONS **
clk : INPUT;
cs4 : INPUT;
cs5 : INPUT;
cs6 : INPUT;
flag : INPUT;
IR_out0 : INPUT;
IR_out1 : INPUT;
IR_out2 : INPUT;
IR_out3 : INPUT;
IR_out4 : INPUT;
IR_out5 : INPUT;
IR_out6 : INPUT;
IR_out7 : INPUT;
-- Node name is 'address_out0'
-- Equation name is 'address_out0', type is output
address_out0 = _LC6_B15;
-- Node name is 'address_out1'
-- Equation name is 'address_out1', type is output
address_out1 = _LC1_B17;
-- Node name is 'address_out2'
-- Equation name is 'address_out2', type is output
address_out2 = _LC5_B24;
-- Node name is 'address_out3'
-- Equation name is 'address_out3', type is output
address_out3 = _LC4_B18;
-- Node name is 'address_out4'
-- Equation name is 'address_out4', type is output
address_out4 = _LC3_B13;
-- Node name is 'address_out5'
-- Equation name is 'address_out5', type is output
address_out5 = _LC3_B15;
-- Node name is 'address_out6'
-- Equation name is 'address_out6', type is output
address_out6 = _LC5_B15;
-- Node name is 'address_out7'
-- Equation name is 'address_out7', type is output
address_out7 = _LC1_B19;
-- Node name is ':66' = 'address0'
-- Equation name is 'address0', location is LC4_B15, type is buried.
address0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cs4 & !cs5 & _LC8_B15
# !address0 & cs4;
-- Node name is ':65' = 'address1'
-- Equation name is 'address1', location is LC6_B17, type is buried.
address1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC8_B17
# address0 & !address1 & cs4
# !address0 & address1 & cs4;
-- Node name is ':64' = 'address2'
-- Equation name is 'address2', location is LC7_B24, type is buried.
address2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_B15 & _LC3_B24
# cs4 & _LC4_B24;
-- Node name is ':63' = 'address3'
-- Equation name is 'address3', location is LC8_B18, type is buried.
address3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC7_B18
# address3 & cs4 & !_LC8_B24
# !address3 & cs4 & _LC8_B24;
-- Node name is ':62' = 'address4'
-- Equation name is 'address4', location is LC8_B13, type is buried.
address4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC7_B13
# address4 & cs4 & !_LC6_B18
# !address4 & cs4 & _LC6_B18;
-- Node name is ':61' = 'address5'
-- Equation name is 'address5', location is LC1_B15, type is buried.
address5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC2_B15 & _LC3_B16
# cs4 & _LC4_B13;
-- Node name is ':60' = 'address6'
-- Equation name is 'address6', location is LC7_B15, type is buried.
address6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC2_B15 & _LC4_B16
# cs4 & _LC8_B19;
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