br.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY BR IS
	PORT
	(	mbr_in	 : IN  std_logic_vector(15 downto 0);
		cs       : IN  std_logic_vector(31 downto 0);
        clk	     : IN  std_logic;
		br_out	 : out std_logic_vector(15 downto 0)
    );
END BR;

ARCHITECTURE behave OF BR IS
BEGIN
	PROCESS(clk)
		BEGIN
			IF clk'event and clk='1' THEN
				if cs(21)='1' then
					br_out<=mbr_in;
				end if;
			END IF;
	END PROCESS;
END behave;