alu.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY ALU IS
	PORT
	(	br_in       :  IN  std_logic_vector(15 downto 0);
		cs          :  IN  std_logic_vector(31 downto 0);
        clk         :  IN  std_logic;
		accis0	    :  OUT std_logic;
		acc         :  OUT std_logic_vector(15 downto 0)
    );
END ALU;

ARCHITECTURE behave OF ALU IS
signal temp:std_logic_vector(15 downto 0);
BEGIN
acc<=temp;
accis0<='1' when temp="0000000000000000" else '0';
	PROCESS(clk)
		BEGIN
			IF clk'event and clk='1' THEN
                if cs(24)='1'  then
                    temp<="0000000000000000";    --reset
				elsif cs(22)='1' then            --add
					temp<=temp+br_in;
				elsif cs(23)='1' then         --sub
					temp<=temp-br_in;
				elsif cs(25)='1' then         --shiftr
					temp<='0'&temp(15 downto 1);
				elsif cs(7)='1' then          --shiftl
					temp<=temp(14 downto 0)&'0';
				elsif cs(1)='1' then          --and
					temp<=temp and br_in;
				elsif cs(2)='1' then          --or
					temp<=temp or br_in;
				elsif cs(3)='1' then          --not
					temp<=not temp;
				end if;
			END IF;
	END PROCESS;
END behave;