📄 cpu.rpt
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- - 8 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_0
- - 1 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_1
- - 8 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_2
- - 3 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_3
- - 2 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_4
- - 6 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_5
- - 6 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_6
- - 5 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_7
- - 1 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_8
- - 5 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_9
- - 3 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_10
- - 7 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_11
- - 2 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_12
- - 7 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_13
- - 4 D -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_14
- - 4 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_DQ:25|altram:sram|segment0_15
- - 4 B -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_0
- - 8 F -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_1
- - 3 F -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_2
- - 2 F -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_3
- - 1 C -- MEM_SGMT 0 8 1 9 |LPM_ROM:2|altrom:srom|segment0_4
- - 4 C -- MEM_SGMT 0 8 1 2 |LPM_ROM:2|altrom:srom|segment0_5
- - 7 C -- MEM_SGMT 0 8 1 10 |LPM_ROM:2|altrom:srom|segment0_6
- - 8 E -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_7
- - 7 B -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_8
- - 2 B -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_9
- - 5 C -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_10
- - 3 C -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_11
- - 7 F -- MEM_SGMT 0 8 1 8 |LPM_ROM:2|altrom:srom|segment0_12
- - 6 F -- MEM_SGMT 0 8 1 8 |LPM_ROM:2|altrom:srom|segment0_13
- - 1 E -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_14
- - 4 F -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_15
- - 5 F -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_16
- - 3 E -- MEM_SGMT 0 8 1 8 |LPM_ROM:2|altrom:srom|segment0_17
- - 4 E -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_18
- - 7 E -- MEM_SGMT 0 8 1 8 |LPM_ROM:2|altrom:srom|segment0_19
- - 6 E -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_20
- - 1 F -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_21
- - 1 B -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_22
- - 8 B -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_23
- - 5 B -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_24
- - 3 B -- MEM_SGMT 0 8 1 16 |LPM_ROM:2|altrom:srom|segment0_25
- - 2 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_26
- - 2 C -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_27
- - 5 E -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_28
- - 6 C -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_29
- - 8 C -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_30
- - 6 B -- MEM_SGMT 0 8 1 0 |LPM_ROM:2|altrom:srom|segment0_31
- 3 - A 18 DFFE + 0 3 0 17 |MAR:17|:50
- 4 - A 07 DFFE + 0 3 0 17 |MAR:17|:52
- 7 - A 10 DFFE + 0 3 0 17 |MAR:17|:54
- 6 - A 12 DFFE + 0 3 0 17 |MAR:17|:56
- 7 - A 11 DFFE + 0 3 0 17 |MAR:17|:58
- 1 - A 02 DFFE + 0 3 0 17 |MAR:17|:60
- 3 - A 04 DFFE + 0 3 0 17 |MAR:17|:62
- 6 - D 09 DFFE + 0 3 0 17 |MAR:17|:64
- 5 - A 18 OR2 0 3 0 1 |MAR:17|:289
- 3 - A 07 OR2 0 3 0 1 |MAR:17|:301
- 2 - A 10 OR2 0 3 0 1 |MAR:17|:310
- 7 - A 12 OR2 0 3 0 1 |MAR:17|:319
- 5 - A 11 OR2 0 3 0 1 |MAR:17|:328
- 4 - A 02 OR2 0 3 0 1 |MAR:17|:337
- 6 - A 04 OR2 0 3 0 1 |MAR:17|:346
- 7 - D 09 OR2 0 3 0 1 |MAR:17|:355
- 7 - D 07 DFFE + 0 3 0 4 |MBR:11|:66
- 4 - D 06 DFFE + 0 3 0 4 |MBR:11|:68
- 8 - D 08 DFFE + 0 3 0 4 |MBR:11|:70
- 2 - D 05 DFFE + 0 3 0 4 |MBR:11|:72
- 8 - D 07 DFFE + 0 3 0 4 |MBR:11|:74
- 1 - D 19 DFFE + 0 3 0 4 |MBR:11|:76
- 5 - D 14 DFFE + 0 3 0 4 |MBR:11|:78
- 8 - D 04 DFFE + 0 3 0 4 |MBR:11|:80
- 2 - A 18 DFFE + 0 3 0 6 |MBR:11|:82
- 7 - A 07 DFFE + 0 3 0 6 |MBR:11|:84
- 8 - A 10 DFFE + 0 3 0 6 |MBR:11|:86
- 1 - A 12 DFFE + 0 3 0 6 |MBR:11|:88
- 4 - A 11 DFFE + 0 3 0 6 |MBR:11|:90
- 3 - A 02 DFFE + 0 3 0 6 |MBR:11|:92
- 5 - A 04 DFFE + 0 3 0 6 |MBR:11|:94
- 2 - D 09 DFFE + 0 3 0 6 |MBR:11|:96
- 3 - D 07 OR2 0 3 0 1 |MBR:11|:401
- 2 - D 06 OR2 0 3 0 1 |MBR:11|:413
- 7 - D 08 OR2 0 3 0 1 |MBR:11|:422
- 4 - D 05 OR2 0 3 0 1 |MBR:11|:431
- 4 - D 07 OR2 0 3 0 1 |MBR:11|:440
- 5 - D 19 OR2 0 3 0 1 |MBR:11|:449
- 3 - D 14 OR2 0 3 0 1 |MBR:11|:458
- 3 - D 04 OR2 0 3 0 1 |MBR:11|:467
- 6 - A 18 OR2 0 3 0 1 |MBR:11|:476
- 5 - A 07 OR2 0 3 0 1 |MBR:11|:485
- 3 - A 10 OR2 0 3 0 1 |MBR:11|:494
- 8 - A 12 OR2 0 3 0 1 |MBR:11|:503
- 6 - A 11 OR2 0 3 0 1 |MBR:11|:512
- 5 - A 02 OR2 0 3 0 1 |MBR:11|:521
- 7 - A 04 OR2 0 3 0 1 |MBR:11|:530
- 8 - D 09 OR2 0 3 0 1 |MBR:11|:539
- 2 - A 08 AND2 0 3 0 4 |PC:20|LPM_ADD_SUB:299|addcore:adder|:125
- 6 - A 06 AND2 0 2 0 1 |PC:20|LPM_ADD_SUB:299|addcore:adder|:129
- 4 - A 06 AND2 0 4 0 2 |PC:20|LPM_ADD_SUB:299|addcore:adder|:137
- 8 - A 03 DFFE + 0 4 1 1 |PC:20|:42
- 6 - A 07 DFFE + 0 4 1 1 |PC:20|:44
- 6 - A 10 DFFE + 0 4 1 1 |PC:20|:46
- 2 - A 12 DFFE + 0 4 1 1 |PC:20|:48
- 1 - A 11 DFFE + 0 4 1 1 |PC:20|:50
- 7 - A 08 DFFE + 0 4 1 1 |PC:20|:52
- 1 - A 08 DFFE + 0 4 1 1 |PC:20|:54
- 6 - A 03 DFFE + 0 4 1 1 |PC:20|:56
- 5 - A 03 DFFE + 0 4 0 1 |PC:20|temp7 (|PC:20|:58)
- 2 - A 03 DFFE + 0 4 0 2 |PC:20|temp6 (|PC:20|:59)
- 7 - A 06 DFFE + 0 4 0 2 |PC:20|temp5 (|PC:20|:60)
- 5 - A 06 DFFE + 0 4 0 3 |PC:20|temp4 (|PC:20|:61)
- 3 - A 06 DFFE + 0 4 0 4 |PC:20|temp3 (|PC:20|:62)
- 6 - A 08 DFFE + 0 4 0 2 |PC:20|temp2 (|PC:20|:63)
- 4 - A 08 DFFE + 0 4 0 3 |PC:20|temp1 (|PC:20|:64)
- 7 - A 03 DFFE + 0 4 0 4 |PC:20|temp0 (|PC:20|:65)
- 4 - A 03 OR2 0 4 0 2 |PC:20|:309
- 3 - A 03 OR2 0 3 0 2 |PC:20|:327
- 8 - A 06 OR2 0 4 0 2 |PC:20|:339
- 1 - A 06 OR2 0 4 0 2 |PC:20|:351
- 2 - A 06 OR2 0 3 0 2 |PC:20|:363
- 5 - A 08 OR2 0 4 0 2 |PC:20|:375
- 3 - A 08 OR2 0 3 0 2 |PC:20|:387
- 1 - A 03 OR2 0 2 0 2 |PC:20|:399
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\max+plus2\cpudesign\cpu.rpt
cpu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 50/ 96( 52%) 34/ 48( 70%) 16/ 48( 33%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 7/ 96( 7%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
C: 12/ 96( 12%) 38/ 48( 79%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 48/ 96( 50%) 33/ 48( 68%) 20/ 48( 41%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
E: 9/ 96( 9%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
F: 9/ 96( 9%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 7/24( 29%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 7/24( 29%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 3/24( 12%) 0/4( 0%)⌨️ 快捷键说明
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