📄 cpu.rpt
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Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 6 8 7 0 8 8 7 8 8 8 8 8 8 1 0 0 8 7 8 0 8 8 8 0 132/8
B: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
C: 8 0 8 0 8 8 7 1 8 1 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 65/8
D: 8 8 8 8 8 8 7 8 8 0 8 1 8 8 8 0 0 0 0 8 8 0 8 8 0 128/8
E: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
F: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0/8
Total: 16 14 24 15 16 24 22 16 24 9 24 17 48 16 9 0 0 8 7 16 8 8 16 16 0 325/48
Device-Specific Information: d:\max+plus2\cpudesign\cpu.rpt
cpu
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\max+plus2\cpudesign\cpu.rpt
cpu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
95 - - B -- OUTPUT 0 1 0 0 o0
98 - - B -- OUTPUT 0 1 0 0 o1
23 - - D -- OUTPUT 0 1 0 0 o2
80 - - F -- OUTPUT 0 1 0 0 o3
13 - - C -- OUTPUT 0 1 0 0 o4
14 - - C -- OUTPUT 0 1 0 0 o5
90 - - C -- OUTPUT 0 1 0 0 o6
10 - - B -- OUTPUT 0 1 0 0 o7
9 - - B -- OUTPUT 0 1 0 0 o8
144 - - A -- OUTPUT 0 1 0 0 o9
91 - - C -- OUTPUT 0 1 0 0 o10
12 - - C -- OUTPUT 0 1 0 0 o11
82 - - E -- OUTPUT 0 1 0 0 o12
18 - - D -- OUTPUT 0 1 0 0 o13
87 - - E -- OUTPUT 0 1 0 0 o14
20 - - D -- OUTPUT 0 1 0 0 o15
22 - - D -- OUTPUT 0 1 0 0 o16
79 - - F -- OUTPUT 0 1 0 0 o17
27 - - E -- OUTPUT 0 1 0 0 o18
29 - - E -- OUTPUT 0 1 0 0 o19
86 - - E -- OUTPUT 0 1 0 0 o20
30 - - F -- OUTPUT 0 1 0 0 o21
88 - - D -- OUTPUT 0 1 0 0 o22
97 - - B -- OUTPUT 0 1 0 0 o23
19 - - D -- OUTPUT 0 1 0 0 o24
21 - - D -- OUTPUT 0 1 0 0 o25
28 - - E -- OUTPUT 0 1 0 0 o26
92 - - C -- OUTPUT 0 1 0 0 o27
101 - - A -- OUTPUT 0 1 0 0 o28
89 - - C -- OUTPUT 0 1 0 0 o29
38 - - - 22 OUTPUT 0 1 0 0 o30
96 - - B -- OUTPUT 0 1 0 0 o31
114 - - - 04 OUTPUT 0 1 0 0 pc0
143 - - A -- OUTPUT 0 1 0 0 pc1
7 - - A -- OUTPUT 0 1 0 0 pc2
109 - - A -- OUTPUT 0 1 0 0 pc3
102 - - A -- OUTPUT 0 1 0 0 pc4
100 - - A -- OUTPUT 0 1 0 0 pc5
83 - - E -- OUTPUT 0 1 0 0 pc6
8 - - A -- OUTPUT 0 1 0 0 pc7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max+plus2\cpudesign\cpu.rpt
cpu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 09 OR2 0 4 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry1
- 3 - A 17 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry2
- 2 - A 23 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry3
- 1 - A 23 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry4
- 3 - A 19 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry5
- 1 - A 19 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry6
- 2 - D 13 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry7
- 7 - D 13 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry8
- 1 - D 22 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry9
- 8 - D 22 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry10
- 3 - D 02 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry11
- 2 - D 02 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry12
- 5 - D 11 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry13
- 8 - D 03 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|pcarry14
- 5 - D 09 OR2 0 2 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:161
- 8 - A 09 OR2 0 4 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:178
- 8 - A 17 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:179
- 7 - A 21 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:180
- 8 - A 23 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:181
- 8 - A 13 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:182
- 8 - A 19 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:183
- 8 - A 22 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:184
- 3 - D 13 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:185
- 4 - D 23 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:186
- 2 - D 22 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:187
- 3 - D 20 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:188
- 4 - D 02 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:189
- 4 - D 11 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:190
- 1 - D 03 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:191
- 8 - D 01 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:859|addcore:adder|:192
- 4 - A 09 OR2 0 4 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry1
- 2 - A 21 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry2
- 1 - A 21 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry3
- 1 - A 13 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry4
- 2 - A 13 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry5
- 3 - A 22 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry6
- 2 - A 22 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry7
- 3 - D 23 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry8
- 2 - D 23 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry9
- 2 - D 20 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry10
- 1 - D 20 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry11
- 1 - D 11 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry12
- 2 - D 11 OR2 0 3 0 2 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry13
- 4 - D 03 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|pcarry14
- 5 - A 09 OR2 s 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|~178~1
- 2 - A 02 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:179
- 5 - A 21 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:180
- 6 - A 23 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:181
- 6 - A 13 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:182
- 6 - A 19 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:183
- 6 - A 22 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:184
- 4 - D 13 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:185
- 5 - D 23 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:186
- 3 - D 22 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:187
- 4 - D 20 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:188
- 5 - D 02 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:189
- 6 - D 11 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:190
- 5 - D 03 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:191
- 3 - D 01 OR2 0 3 0 1 |ALU:29|LPM_ADD_SUB:972|addcore:adder|:192
- 2 - D 01 DFFE + 0 4 0 7 |ALU:29|temp15 (|ALU:29|:67)
- 2 - D 03 DFFE + 0 4 0 10 |ALU:29|temp14 (|ALU:29|:68)
- 3 - D 11 DFFE + 0 4 0 10 |ALU:29|temp13 (|ALU:29|:69)
- 1 - D 02 DFFE + 0 4 0 10 |ALU:29|temp12 (|ALU:29|:70)
- 6 - D 20 DFFE + 0 4 0 10 |ALU:29|temp11 (|ALU:29|:71)
- 5 - D 22 DFFE + 0 4 0 10 |ALU:29|temp10 (|ALU:29|:72)
- 1 - D 23 DFFE + 0 4 0 10 |ALU:29|temp9 (|ALU:29|:73)
- 1 - D 13 DFFE + 0 4 0 10 |ALU:29|temp8 (|ALU:29|:74)
- 1 - A 22 DFFE + 0 4 0 10 |ALU:29|temp7 (|ALU:29|:75)
- 2 - A 19 DFFE + 0 4 0 10 |ALU:29|temp6 (|ALU:29|:76)
- 4 - A 13 DFFE + 0 4 0 10 |ALU:29|temp5 (|ALU:29|:77)
- 4 - A 23 DFFE + 0 4 0 10 |ALU:29|temp4 (|ALU:29|:78)
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