📄 cpu.rpt
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Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S G G G G V S S S S S S S S S S S
E E E G E E E E V E E E E G E N N N N C E E E E E E E V E E E E
R R R N R R R R C R R R R N R D D D D C R R R R R R R C R R R R
p V V V D V V V V C V V V V D V I I I I I V V V V V V V C p V V V V p
o c E E E I E E E E I E E E E I E N N N N N E E E E E E E I c E E E E c
9 1 D D D O D D D D O D D D D O D T T T T T D D D D D D D O 0 D D D D 3
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
pc2 | 7 102 | pc4
pc7 | 8 101 | o28
o8 | 9 100 | pc5
o7 | 10 99 | RESERVED
RESERVED | 11 98 | o1
o11 | 12 97 | o23
o4 | 13 96 | o31
o5 | 14 95 | o0
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | o27
o13 | 18 91 | o10
o24 | 19 EPF10K20TC144-3 90 | o6
o15 | 20 89 | o29
o25 | 21 88 | o22
o16 | 22 87 | o14
o2 | 23 86 | o20
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | pc6
o18 | 27 82 | o12
o26 | 28 81 | RESERVED
o19 | 29 80 | o3
o21 | 30 79 | o17
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R o R G R R R R V R R R R G R V V G c G G G R R V R R R R G R R R R V R
E 3 E N E E E E C E E E E N E C C N l N N N E E C E E E E N E E E E C E
S 0 S D S S S S C S S S S D S C C D k D D D S S C S S S S D S S S S C S
E E I E E E E I E E E E I E I I I I I I E E I E E E E I E E E E I E
R R O R R R R O R R R R O R N N N N N N R R O R R R R O R R R R O R
V V V V V V V V V V V T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\max+plus2\cpudesign\cpu.rpt
cpu
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A2 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
A3 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
A4 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
A6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A7 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 13/22( 59%)
A8 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A9 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
A10 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 13/22( 59%)
A11 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 13/22( 59%)
A12 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 13/22( 59%)
A13 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
A14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A17 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 13/22( 59%)
A18 7/ 8( 87%) 2/ 8( 25%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
A19 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
A21 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
A22 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 12/22( 54%)
A23 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
C1 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 6/22( 27%)
C3 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 15/22( 68%)
C5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
C6 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
C7 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 9/22( 40%)
C8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
C9 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 7/22( 31%)
C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C11 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 17/22( 77%)
C12 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 16/22( 72%)
D1 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 13/22( 59%)
D2 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
D3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 10/22( 45%)
D4 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
D5 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 12/22( 54%)
D6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 16/22( 72%)
D7 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 10/22( 45%)
D8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 12/22( 54%)
D9 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
D11 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
D12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
D13 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
D14 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 17/22( 77%)
D19 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 11/22( 50%)
D20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
D22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
D23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 2/8 ( 25%) 6/8 ( 75%) 1/2 2/2 17/22( 77%)
B25 8/8 (100%) 5/8 ( 62%) 5/8 ( 62%) 0/2 2/2 8/22( 36%)
C25 8/8 (100%) 1/8 ( 12%) 8/8 (100%) 0/2 2/2 8/22( 36%)
D25 8/8 (100%) 1/8 ( 12%) 7/8 ( 87%) 1/2 2/2 17/22( 77%)
E25 8/8 (100%) 9/8 (112%) 7/8 ( 87%) 0/2 2/2 8/22( 36%)
F25 8/8 (100%) 10/8 (125%) 8/8 (100%) 0/2 2/2 8/22( 36%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 40/96 ( 41%)
Total logic cells used: 325/1152 ( 28%)
Total embedded cells used: 48/48 (100%)
Total EABs used: 6/6 (100%)
Average fan-in: 3.36/4 ( 84%)
Total fan-in: 1093/4608 ( 23%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 40
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 325
Total flipflops required: 88
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 23/1152 ( 1%)
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