📄 alu.rpt
字号:
43 - - - -- INPUT 0 0 0 16 cs25
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\cpu\alu.rpt
alu
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
58 - - C -- OUTPUT 0 1 0 0 accis0
83 - - - 13 OUTPUT 0 1 0 0 acc0
79 - - - 24 OUTPUT 0 1 0 0 acc1
62 - - C -- OUTPUT 0 1 0 0 acc2
60 - - C -- OUTPUT 0 1 0 0 acc3
59 - - C -- OUTPUT 0 1 0 0 acc4
30 - - C -- OUTPUT 0 1 0 0 acc5
61 - - C -- OUTPUT 0 1 0 0 acc6
47 - - - 14 OUTPUT 0 1 0 0 acc7
78 - - - 24 OUTPUT 0 1 0 0 acc8
72 - - A -- OUTPUT 0 1 0 0 acc9
71 - - A -- OUTPUT 0 1 0 0 acc10
17 - - A -- OUTPUT 0 1 0 0 acc11
16 - - A -- OUTPUT 0 1 0 0 acc12
19 - - A -- OUTPUT 0 1 0 0 acc13
18 - - A -- OUTPUT 0 1 0 0 acc14
38 - - - 10 OUTPUT 0 1 0 0 acc15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\cpu\alu.rpt
alu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 23 OR2 2 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry1
- 3 - C 15 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry2
- 1 - C 24 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry3
- 6 - C 24 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry4
- 1 - C 17 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry5
- 8 - C 17 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry6
- 2 - A 23 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry7
- 4 - A 23 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry8
- 1 - A 15 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry9
- 7 - A 15 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry10
- 2 - A 03 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry11
- 4 - A 03 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry12
- 1 - A 10 OR2 1 2 0 2 |LPM_ADD_SUB:859|addcore:adder|pcarry13
- 3 - A 10 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|pcarry14
- 7 - A 14 OR2 1 1 0 1 |LPM_ADD_SUB:859|addcore:adder|:161
- 7 - C 23 OR2 2 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:178
- 8 - C 15 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:179
- 3 - C 18 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:180
- 2 - C 24 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:181
- 1 - C 20 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:182
- 2 - C 17 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:183
- 3 - C 14 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:184
- 3 - A 23 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:185
- 1 - A 22 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:186
- 2 - A 15 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:187
- 1 - A 21 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:188
- 3 - A 03 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:189
- 1 - A 07 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:190
- 2 - A 10 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:191
- 8 - A 09 OR2 1 2 0 1 |LPM_ADD_SUB:859|addcore:adder|:192
- 8 - C 23 OR2 2 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry1
- 6 - C 15 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry2
- 1 - C 18 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry3
- 3 - C 20 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry4
- 2 - C 20 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry5
- 4 - C 14 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry6
- 1 - C 14 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry7
- 3 - A 22 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry8
- 5 - A 22 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry9
- 2 - A 21 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry10
- 8 - A 21 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry11
- 2 - A 07 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry12
- 8 - A 07 OR2 1 2 0 2 |LPM_ADD_SUB:972|addcore:adder|pcarry13
- 6 - A 10 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|pcarry14
- 4 - C 23 OR2 s 2 1 0 1 |LPM_ADD_SUB:972|addcore:adder|~178~1
- 5 - C 15 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:179
- 7 - C 18 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:180
- 3 - C 24 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:181
- 4 - C 20 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:182
- 4 - C 17 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:183
- 5 - C 14 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:184
- 5 - A 23 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:185
- 4 - A 22 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:186
- 3 - A 15 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:187
- 4 - A 21 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:188
- 5 - A 03 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:189
- 3 - A 07 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:190
- 4 - A 10 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:191
- 1 - A 09 OR2 1 2 0 1 |LPM_ADD_SUB:972|addcore:adder|:192
- 2 - A 09 DFFE + 2 2 1 6 temp15 (:67)
- 8 - A 10 DFFE + 2 2 1 9 temp14 (:68)
- 7 - A 07 DFFE + 2 2 1 9 temp13 (:69)
- 1 - A 03 DFFE + 2 2 1 9 temp12 (:70)
- 3 - A 21 DFFE + 2 2 1 9 temp11 (:71)
- 4 - A 15 DFFE + 2 2 1 9 temp10 (:72)
- 2 - A 22 DFFE + 2 2 1 9 temp9 (:73)
- 1 - A 23 DFFE + 2 2 1 9 temp8 (:74)
- 2 - C 14 DFFE + 2 2 1 9 temp7 (:75)
- 3 - C 17 DFFE + 2 2 1 9 temp6 (:76)
- 6 - C 20 DFFE + 2 2 1 9 temp5 (:77)
- 8 - C 24 DFFE + 2 2 1 9 temp4 (:78)
- 4 - C 18 DFFE + 2 2 1 9 temp3 (:79)
- 1 - C 15 DFFE + 2 2 1 9 temp2 (:80)
- 5 - C 23 DFFE + 2 2 1 9 temp1 (:81)
- 4 - A 14 DFFE + 2 2 1 10 temp0 (:82)
- 3 - A 09 OR2 3 1 0 1 :1624
- 5 - A 09 OR2 2 2 0 1 :1630
- 6 - A 09 OR2 1 2 0 1 :1636
- 7 - A 09 OR2 2 2 0 1 :1648
- 7 - A 06 OR2 3 1 0 1 :1669
- 8 - A 06 OR2 2 2 0 1 :1672
- 1 - A 06 OR2 1 2 0 1 :1675
- 4 - A 09 OR2 1 2 0 1 :1678
- 5 - A 10 OR2 1 2 0 1 :1681
- 6 - A 06 OR2 3 1 0 1 :1696
- 5 - A 06 OR2 2 2 0 1 :1699
- 4 - A 07 OR2 1 2 0 1 :1702
- 5 - A 07 OR2 1 2 0 1 :1705
- 6 - A 07 OR2 1 2 0 1 :1708
- 4 - A 06 OR2 3 1 0 1 :1723
- 2 - A 06 OR2 2 2 0 1 :1726
- 6 - A 03 OR2 1 2 0 1 :1729
- 7 - A 03 OR2 1 2 0 1 :1732
- 8 - A 03 OR2 1 2 0 1 :1735
- 8 - A 14 OR2 3 1 0 1 :1750
- 2 - A 14 OR2 2 2 0 1 :1753
- 5 - A 21 OR2 1 2 0 1 :1756
- 6 - A 21 OR2 1 2 0 1 :1759
- 7 - A 21 OR2 1 2 0 1 :1762
- 6 - A 16 OR2 3 1 0 1 :1777
- 7 - A 16 OR2 2 2 0 1 :1780
- 3 - A 16 OR2 1 2 0 1 :1783
- 5 - A 15 OR2 1 2 0 1 :1786
- 6 - A 15 OR2 1 2 0 1 :1789
- 5 - A 16 OR2 3 1 0 1 :1804
- 1 - A 16 OR2 2 2 0 1 :1807
- 6 - A 22 OR2 1 2 0 1 :1810
- 7 - A 22 OR2 1 2 0 1 :1813
- 8 - A 22 OR2 1 2 0 1 :1816
- 4 - A 16 OR2 3 1 0 1 :1831
- 8 - A 16 OR2 2 2 0 1 :1834
- 6 - A 23 OR2 1 2 0 1 :1837
- 7 - A 23 OR2 1 2 0 1 :1840
- 8 - A 23 OR2 1 2 0 1 :1843
- 7 - C 22 OR2 3 1 0 1 :1858
- 8 - C 22 OR2 2 2 0 1 :1861
- 6 - C 14 OR2 1 2 0 1 :1864
- 7 - C 14 OR2 1 2 0 1 :1867
- 8 - C 14 OR2 1 2 0 1 :1870
- 6 - C 22 OR2 3 1 0 1 :1885
- 2 - C 22 OR2 2 2 0 1 :1888
- 5 - C 17 OR2 1 2 0 1 :1891
- 6 - C 17 OR2 1 2 0 1 :1894
- 7 - C 17 OR2 1 2 0 1 :1897
- 2 - C 13 OR2 3 1 0 1 :1912
- 8 - C 13 OR2 2 2 0 1 :1915
- 5 - C 20 OR2 1 2 0 1 :1918
- 7 - C 20 OR2 1 2 0 1 :1921
- 8 - C 20 OR2 1 2 0 1 :1924
- 5 - C 22 OR2 3 1 0 1 :1939
- 1 - C 22 OR2 2 2 0 1 :1942
- 4 - C 24 OR2 1 2 0 1 :1945
- 5 - C 24 OR2 1 2 0 1 :1948
- 7 - C 24 OR2 1 2 0 1 :1951
- 4 - C 22 OR2 3 1 0 1 :1966
- 3 - C 22 OR2 2 2 0 1 :1969
- 5 - C 18 OR2 1 2 0 1 :1972
- 6 - C 18 OR2 1 2 0 1 :1975
- 8 - C 18 OR2 1 2 0 1 :1978
- 2 - C 15 OR2 3 1 0 1 :1993
- 4 - C 15 OR2 2 2 0 1 :1996
- 3 - C 13 OR2 1 2 0 1 :1999
- 2 - C 18 OR2 1 2 0 1 :2002
- 7 - C 15 OR2 1 2 0 1 :2005
- 1 - C 13 OR2 3 1 0 1 :2020
- 6 - C 13 OR2 2 2 0 1 :2023
- 1 - C 23 OR2 1 2 0 1 :2026
- 2 - C 23 OR2 1 2 0 1 :2029
- 6 - C 23 OR2 1 3 0 1 :2032
- 1 - A 14 OR2 3 1 0 1 :2047
- 3 - A 14 OR2 2 2 0 1 :2050
- 5 - A 14 OR2 2 2 0 1 :2056
- 6 - A 14 OR2 2 2 0 1 :2059
- 3 - A 06 AND2 s 0 4 0 1 ~2235~1
- 2 - A 16 AND2 s 0 4 0 1 ~2235~2
- 4 - C 13 AND2 s 0 4 0 1 ~2235~3
- 5 - C 13 AND2 s 0 4 0 1 ~2235~4
- 7 - C 13 AND2 0 4 1 0 :2235
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\cpu\alu.rpt
alu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 14/ 96( 14%) 13/ 48( 27%) 18/ 48( 37%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 16/ 96( 16%) 0/ 48( 0%) 27/ 48( 56%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\cpu\alu.rpt
alu
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