one.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY WE IS
  PORT (
         C : in  std_logic_vector(31 downto 0); 
          w : out std_logic
       );
  end WE;
 
architecture behave of WE is
   begin
     w<=C(23);
end behave;