📄 mar.rpt
字号:
- 3 - B 18 OR2 2 1 0 1 :355
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: q:\information\cpu2\mar.rpt
mar
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 7/ 48( 14%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
B: 7/ 96( 7%) 0/ 48( 0%) 2/ 48( 4%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: q:\information\cpu2\mar.rpt
mar
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: q:\information\cpu2\mar.rpt
mar
** EQUATIONS **
clk : INPUT;
cs12 : INPUT;
cs13 : INPUT;
mbr0 : INPUT;
mbr1 : INPUT;
mbr2 : INPUT;
mbr3 : INPUT;
mbr4 : INPUT;
mbr5 : INPUT;
mbr6 : INPUT;
mbr7 : INPUT;
pc0 : INPUT;
pc1 : INPUT;
pc2 : INPUT;
pc3 : INPUT;
pc4 : INPUT;
pc5 : INPUT;
pc6 : INPUT;
pc7 : INPUT;
-- Node name is 'mar_out0'
-- Equation name is 'mar_out0', type is output
mar_out0 = _LC7_B18;
-- Node name is 'mar_out1'
-- Equation name is 'mar_out1', type is output
mar_out1 = _LC2_B18;
-- Node name is 'mar_out2'
-- Equation name is 'mar_out2', type is output
mar_out2 = _LC5_B18;
-- Node name is 'mar_out3'
-- Equation name is 'mar_out3', type is output
mar_out3 = _LC1_B18;
-- Node name is 'mar_out4'
-- Equation name is 'mar_out4', type is output
mar_out4 = _LC1_A13;
-- Node name is 'mar_out5'
-- Equation name is 'mar_out5', type is output
mar_out5 = _LC3_A13;
-- Node name is 'mar_out6'
-- Equation name is 'mar_out6', type is output
mar_out6 = _LC5_A13;
-- Node name is 'mar_out7'
-- Equation name is 'mar_out7', type is output
mar_out7 = _LC4_A13;
-- Node name is ':50'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !cs12 & _LC8_A13
# cs12 & pc7;
-- Node name is ':52'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !cs12 & _LC7_A13
# cs12 & pc6;
-- Node name is ':54'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !cs12 & _LC6_A13
# cs12 & pc5;
-- Node name is ':56'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !cs12 & _LC2_A13
# cs12 & pc4;
-- Node name is ':58'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !cs12 & _LC8_B18
# cs12 & pc3;
-- Node name is ':60'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !cs12 & _LC6_B18
# cs12 & pc2;
-- Node name is ':62'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !cs12 & _LC4_B18
# cs12 & pc1;
-- Node name is ':64'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !cs12 & _LC3_B18
# cs12 & pc0;
-- Node name is ':289'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ009);
_EQ009 = !cs13 & _LC4_A13
# cs13 & mbr7;
-- Node name is ':301'
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ010);
_EQ010 = !cs13 & _LC5_A13
# cs13 & mbr6;
-- Node name is ':310'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = LCELL( _EQ011);
_EQ011 = !cs13 & _LC3_A13
# cs13 & mbr5;
-- Node name is ':319'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = LCELL( _EQ012);
_EQ012 = !cs13 & _LC1_A13
# cs13 & mbr4;
-- Node name is ':328'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ013);
_EQ013 = !cs13 & _LC1_B18
# cs13 & mbr3;
-- Node name is ':337'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ014);
_EQ014 = !cs13 & _LC5_B18
# cs13 & mbr2;
-- Node name is ':346'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ015);
_EQ015 = !cs13 & _LC2_B18
# cs13 & mbr1;
-- Node name is ':355'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = LCELL( _EQ016);
_EQ016 = !cs13 & _LC7_B18
# cs13 & mbr0;
Project Information q:\information\cpu2\mar.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,607K
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