mar.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAR is
port(
      clk:in std_logic;
      PC_in: in std_logic_vector(7 downto 0);
      MBR_in: in std_logic_vector(7 downto 0);
      MAR_out: out std_logic_vector(7 downto 0);
      C: in std_logic_vector(31 downto 0)
);
end MAR;
architecture MAR_behave of MAR is
begin
  process(clk)
   begin
    if clk'event and clk='1' then
      if C(5)='1' then
        MAR_out<=MBR_in;
     elsif C(10)='1' then
       MAR_out<=PC_in;
     end if;
   end if;
 end process;
end MAR_behave;