ram.map.rpt

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; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource                       ; Usage      ;
+--------------------------------+------------+
; Total logic elements           ; 0          ;
; Total combinational functions  ; 0          ;
;     -- Total 4-input functions ; 0          ;
;     -- Total 3-input functions ; 0          ;
;     -- Total 2-input functions ; 0          ;
;     -- Total 1-input functions ; 0          ;
;     -- Total 0-input functions ; 0          ;
; Total registers                ; 0          ;
; I/O pins                       ; 42         ;
; Total memory bits              ; 4096       ;
; Maximum fan-out node           ; inclock    ;
; Maximum fan-out                ; 16         ;
; Total fan-out                  ; 192        ;
; Average fan-out                ; 3.31       ;
+--------------------------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                               ;
+-----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node              ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                               ; Library Name ;
+-----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------+--------------+
; |RAM                                    ; 0 (0)       ; 0            ; 4096        ; 42   ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM                                                              ; work         ;
;    |lpm_ram_dq0:inst|                   ; 0 (0)       ; 0            ; 4096        ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM|lpm_ram_dq0:inst                                             ; work         ;
;       |lpm_ram_dq:lpm_ram_dq_component| ; 0 (0)       ; 0            ; 4096        ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component             ; work         ;
;          |altram:sram|                  ; 0 (0)       ; 0            ; 4096        ; 0    ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |RAM|lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram ; work         ;
+-----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                ;
+----------------------------------------------------------------------+-------------+--------------+--------------+--------------+--------------+------+---------+
; Name                                                                 ; Mode        ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF     ;
+----------------------------------------------------------------------+-------------+--------------+--------------+--------------+--------------+------+---------+
; lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram|content ; Single Port ; 256          ; 16           ; --           ; --           ; 4096 ; RAM.mif ;
+----------------------------------------------------------------------+-------------+--------------+--------------+--------------+--------------+------+---------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component ;
+------------------------+--------------+-------------------------------------------------------+
; Parameter Name         ; Value        ; Type                                                  ;
+------------------------+--------------+-------------------------------------------------------+
; LPM_WIDTH              ; 16           ; Signed Integer                                        ;
; LPM_WIDTHAD            ; 8            ; Signed Integer                                        ;
; LPM_NUMWORDS           ; 256          ; Untyped                                               ;
; LPM_INDATA             ; UNREGISTERED ; Untyped                                               ;
; LPM_ADDRESS_CONTROL    ; REGISTERED   ; Untyped                                               ;
; LPM_OUTDATA            ; UNREGISTERED ; Untyped                                               ;
; LPM_FILE               ; RAM.mif      ; Untyped                                               ;
; USE_EAB                ; ON           ; Untyped                                               ;
; DEVICE_FAMILY          ; FLEX10K      ; Untyped                                               ;
; CBXI_PARAMETER         ; NOTHING      ; Untyped                                               ;
; AUTO_CARRY_CHAINS      ; ON           ; AUTO_CARRY                                            ;
; IGNORE_CARRY_BUFFERS   ; OFF          ; IGNORE_CARRY                                          ;
; AUTO_CASCADE_CHAINS    ; ON           ; AUTO_CASCADE                                          ;
; IGNORE_CASCADE_BUFFERS ; OFF          ; IGNORE_CASCADE                                        ;
+------------------------+--------------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Mon Apr 21 11:08:19 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM -c RAM
Info: Found 1 design units, including 1 entities, in source file RAM.bdf
    Info: Found entity 1: RAM
Info: Elaborating entity "RAM" for the top level hierarchy
Warning: Using design file lpm_ram_dq0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_ram_dq0-SYN
    Info: Found entity 1: lpm_ram_dq0
Info: Elaborating entity "lpm_ram_dq0" for hierarchy "lpm_ram_dq0:inst"
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf
    Info: Found entity 1: lpm_ram_dq
Info: Elaborating entity "lpm_ram_dq" for hierarchy "lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component"
Info: Elaborated megafunction instantiation "lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component"
Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf
    Info: Found entity 1: altram
Info: Elaborating entity "altram" for hierarchy "lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram"
Info: Elaborated megafunction instantiation "lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component|altram:sram", which is child of megafunction instantiation "lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component"
Info: Instantiated megafunction "lpm_ram_dq0:inst|lpm_ram_dq:lpm_ram_dq_component" with the following parameter:
    Info: Parameter "lpm_address_control" = "REGISTERED"
    Info: Parameter "lpm_file" = "RAM.mif"
    Info: Parameter "lpm_indata" = "UNREGISTERED"
    Info: Parameter "lpm_outdata" = "UNREGISTERED"
    Info: Parameter "lpm_type" = "LPM_RAM_DQ"
    Info: Parameter "lpm_width" = "16"
    Info: Parameter "lpm_widthad" = "8"
Info: Implemented 58 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 16 output pins
    Info: Implemented 16 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 149 megabytes of memory during processing
    Info: Processing ended: Mon Apr 21 11:08:22 2008
    Info: Elapsed time: 00:00:03