change2.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY change2 IS
  PORT (
         MBR_in : in  std_logic_vector(15 downto 0);
         q      : out std_logic_vector(7 downto 0)     --IR
       );
  end change2;
 
architecture behave of change2 is
   begin
     q(0)<=MBR_in(8);
     q(1)<=MBR_in(9);
     q(2)<=MBR_in(10);
     q(3)<=MBR_in(11);
     q(4)<=MBR_in(12);
     q(5)<=MBR_in(13);
     q(6)<=MBR_in(14);
     q(7)<=MBR_in(15);
end behave;