alu.vhd

来自「实现简单CPU功能的源码」· VHDL 代码 · 共 44 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU is
port (
        clk : in std_logic;
        BR_out: in std_logic_vector(15 downto 0);
        C : in std_logic_vector(31 downto 0);
        ACC_in : out std_logic_vector(15 downto 0);
        MUL:out std_logic_vector(31 downto 0)
);
end ALU;
architecture ALU_behave of ALU is
signal A:std_logic_vector(15 downto 0);
begin
    ACC_in<=A;
process(clk)
begin
   if clk'event and clk='1' then
      if C(8)='1' then
        A<="0000000000000000";              --reset
      elsif C(9)='1' then
        A<=A+BR_out;                  --add
      elsif C(11)='1' then
        A<=A-BR_out;                  --sub
      elsif C(12)='1' then
        A<=A and BR_out;              --and
      elsif C(13)='1' then
        A<=A or BR_out;               --or
      elsif C(14)='1' then
        A<=not A;                     --not
      elsif C(15)='1' then
        A<=BR_out(14 downto 0) & '0';        --SRL
      elsif C(16)='1' then
        A<='0' & BR_out(15 downto 1);        --SRR
      elsif C(22)='1' then             --mul
        MUL<=A*BR_OUT;
      end if;
    end if;
 end process;
end ALU_behave;