acc.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ACC is
port(
      clk: in std_logic;
      ACC_in: in std_logic_vector(15 downto 0);
      ACC_out: out std_logic_vector(15 downto 0);
      flag: out std_logic;
      C: in std_logic
);
end ACC;
architecture ACC_behave of ACC is
begin
  
  process(clk)
   begin
  if clk'event and clk='1' then
     if C='1' then
        ACC_out<="0000000000000000";
	else
		ACC_out<=ACC_in;
     end if;
	 if ACC_in(15)='0'then 
	flag<='1';
	else flag<='0';
end if;
  end if;
end process;
end ACC_behave;