c.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity C is
port(
      clk: in std_logic;
      C: in std_logic_vector(31 downto 0);
      flag: in std_logic;   --the highest symbol of ACC is '0' or not
      IR_in: in std_logic_vector(7 downto 0);
      address_out: out std_logic_vector(7 downto 0)
);
end C;
architecture C_behave of C is
begin
  process(clk)
variable address: std_logic_vector(7 downto 0);
    begin
     if clk'event and clk='1' then
 
       if C(0)='1' then
         address:=address+1;   --CAR<=CAR+1
       elsif C(2)='1' then
         address:="00000000";   --CAR<=0
       elsif C(1)='1' then     --CAR<=***
          case IR_in is
 --           when "00000000"=>   --fetch
 --            address:="00000000";
            when "00000001"=>  --load
             address:=x"08";
            when "00000010"=>  --store
              address:=x"10";
            when "00000011"=>  --add
              address:=x"16";
            when "00000100"=>  --sub
              address:=x"20";
            when "00000101"=>  --jmpgez
              if flag='1' then
              address:=x"70";
              else address:=x"72";
              end if;
            when "00000110"=>  --jmp
              address:=x"70";
            when "00000111"=>  --halt
              address:=x"30";
            when "00001000"=>  --and
              address:=x"32";
            when "00001001"=>  --or
              address:=x"3C";
            when "00001010"=>  --not
              address:=x"45";
            when "00001011"=>  --shifter
              address:=x"50";
            when "00001100"=>  --shiftel
              address:=x"60";
            when "00001101"=>  --mul
              address:=x"80";
            when others=>
              null;
         end case;
       end if;
       address_out<=address;
     end if;
 end process;
end C_behave;