pc.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is
port(
     clk: in std_logic;
     PC_in: in std_logic_vector(7 downto 0);
     PC_out: out std_logic_vector(7 downto 0);
     C: in std_logic_vector(31 downto 0)
);
end PC;
architecture PC_behave of PC is
signal p: std_logic_vector(7 downto 0);
begin
   process(clk)
    begin
           PC_out<=p;
     if clk'event and clk='1' then
       if C(6)='1' then
         p<=p+1;
       elsif C(24)='1' then
         p<=PC_in;
       elsif C(19)='1' then
        p<="00000000";
       end if;
     end if;
  end process;
end PC_behave;