prev_cmp_cpu.qmsg

实现简单CPU功能的源码

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[1\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[1\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[2\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[2\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[3\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[3\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[4\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[4\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[5\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[5\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[6\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[6\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[7\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[7\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[8\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[8\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[9\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[9\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[10\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[10\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[11\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[11\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[12\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[12\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[13\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[13\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[14\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[14\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[15\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[15\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALU ALU:inst5 " "Info: Elaborating entity \"ALU\" for hierarchy \"ALU:inst5\"" {  } { { "CPU.bdf" "inst5" { Schematic "D:/CPU/CPU.bdf" { { -40 1128 1320 56 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BR BR:inst3 " "Info: Elaborating entity \"BR\" for hierarchy \"BR:inst3\"" {  } { { "CPU.bdf" "inst3" { Schematic "D:/CPU/CPU.bdf" { { -184 784 968 -88 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ALU:inst5\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add0\"" {  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ALU:inst5\|lpm_add_sub:Add0\|addcore:adder ALU:inst5\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"ALU:inst5\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ALU:inst5\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"ALU:inst5\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 16 " "Info: Parameter \"LPM_WIDTH\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/program files/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}