prev_cmp_cpu.qmsg

实现简单CPU功能的源码

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_rom1:inst10\|lpm_rom:lpm_rom_component " "Info: Instantiated megafunction \"lpm_rom1:inst10\|lpm_rom:lpm_rom_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family FLEX10K " "Info: Parameter \"intended_device_family\" = \"FLEX10K\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control UNREGISTERED " "Info: Parameter \"lpm_address_control\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_file rom.mif " "Info: Parameter \"lpm_file\" = \"rom.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata UNREGISTERED " "Info: Parameter \"lpm_outdata\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ROM " "Info: Parameter \"lpm_type\" = \"LPM_ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 32 " "Info: Parameter \"lpm_width\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 8 " "Info: Parameter \"lpm_widthad\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "lpm_rom1.vhd" "" { Text "D:/CPU/lpm_rom1.vhd" 76 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "C C:inst9 " "Info: Elaborating entity \"C\" for hierarchy \"C:inst9\"" {  } { { "CPU.bdf" "inst9" { Schematic "D:/CPU/CPU.bdf" { { 256 784 976 384 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "IR IR:inst2 " "Info: Elaborating entity \"IR\" for hierarchy \"IR:inst2\"" {  } { { "CPU.bdf" "inst2" { Schematic "D:/CPU/CPU.bdf" { { -40 792 960 56 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MBR MBR:inst8 " "Info: Elaborating entity \"MBR\" for hierarchy \"MBR:inst8\"" {  } { { "CPU.bdf" "inst8" { Schematic "D:/CPU/CPU.bdf" { { -200 392 608 -72 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_ram_dq0.vhd 2 1 " "Warning: Using design file lpm_ram_dq0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_ram_dq0-SYN " "Info: Found design unit 1: lpm_ram_dq0-SYN" {  } { { "lpm_ram_dq0.vhd" "" { Text "D:/CPU/lpm_ram_dq0.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq0 " "Info: Found entity 1: lpm_ram_dq0" {  } { { "lpm_ram_dq0.vhd" "" { Text "D:/CPU/lpm_ram_dq0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq0 lpm_ram_dq0:inst " "Info: Elaborating entity \"lpm_ram_dq0\" for hierarchy \"lpm_ram_dq0:inst\"" {  } { { "CPU.bdf" "inst" { Schematic "D:/CPU/CPU.bdf" { { -40 424 584 80 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq " "Info: Found entity 1: lpm_ram_dq" {  } { { "lpm_ram_dq.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 60 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborating entity \"lpm_ram_dq\" for hierarchy \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "lpm_ram_dq0.vhd" "lpm_ram_dq_component" { Text "D:/CPU/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborated megafunction instantiation \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "lpm_ram_dq0.vhd" "" { Text "D:/CPU/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altram " "Info: Found entity 1: altram" {  } { { "altram.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altram.tdf" 90 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altram lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram " "Info: Elaborating entity \"altram\" for hierarchy \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\"" {  } { { "lpm_ram_dq.tdf" "sram" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Elaborated megafunction instantiation \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\|altram:sram\", which is child of megafunction instantiation \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\"" {  } { { "lpm_ram_dq.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_ram_dq.tdf" 101 6 0 } } { "lpm_ram_dq0.vhd" "" { Text "D:/CPU/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component " "Info: Instantiated megafunction \"lpm_ram_dq0:inst\|lpm_ram_dq:lpm_ram_dq_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_address_control REGISTERED " "Info: Parameter \"lpm_address_control\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_file RAM.mif " "Info: Parameter \"lpm_file\" = \"RAM.mif\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_indata REGISTERED " "Info: Parameter \"lpm_indata\" = \"REGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_outdata UNREGISTERED " "Info: Parameter \"lpm_outdata\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_RAM_DQ " "Info: Parameter \"lpm_type\" = \"LPM_RAM_DQ\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 16 " "Info: Parameter \"lpm_width\" = \"16\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthad 8 " "Info: Parameter \"lpm_widthad\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "lpm_ram_dq0.vhd" "" { Text "D:/CPU/lpm_ram_dq0.vhd" 82 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MAR MAR:inst13 " "Info: Elaborating entity \"MAR\" for hierarchy \"MAR:inst13\"" {  } { { "CPU.bdf" "inst13" { Schematic "D:/CPU/CPU.bdf" { { 120 416 600 248 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PC PC:inst12 " "Info: Elaborating entity \"PC\" for hierarchy \"PC:inst12\"" {  } { { "CPU.bdf" "inst12" { Schematic "D:/CPU/CPU.bdf" { { 88 800 968 184 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "p PC.vhd(17) " "Warning (10492): VHDL Process Statement warning at PC.vhd(17): signal \"p\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "PC.vhd" "" { Text "D:/CPU/PC.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "change change:inst1 " "Info: Elaborating entity \"change\" for hierarchy \"change:inst1\"" {  } { { "CPU.bdf" "inst1" { Schematic "D:/CPU/CPU.bdf" { { 288 400 608 384 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C change.vhd(16) " "Warning (10492): VHDL Process Statement warning at change.vhd(16): signal \"C\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 16 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MUL_in change.vhd(17) " "Warning (10492): VHDL Process Statement warning at change.vhd(17): signal \"MUL_in\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 17 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C change.vhd(18) " "Warning (10492): VHDL Process Statement warning at change.vhd(18): signal \"C\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 18 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MUL_in change.vhd(19) " "Warning (10492): VHDL Process Statement warning at change.vhd(19): signal \"MUL_in\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 19 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "MUL_OUT change.vhd(14) " "Warning (10631): VHDL Process Statement warning at change.vhd(14): inferring latch(es) for signal or variable \"MUL_OUT\", which holds its previous value in one or more paths through the process" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "MUL_OUT\[0\] change.vhd(14) " "Info (10041): Inferred latch for \"MUL_OUT\[0\]\" at change.vhd(14)" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}