prev_cmp_cpu.qmsg

实现简单CPU功能的源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 28 14:03:41 2008 " "Info: Processing started: Mon Apr 28 14:03:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CPU -c CPU --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CPU -c CPU --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ACC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ACC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ACC-ACC_behave " "Info: Found design unit 1: ACC-ACC_behave" {  } { { "ACC.vhd" "" { Text "D:/CPU/ACC.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ACC " "Info: Found entity 1: ACC" {  } { { "ACC.vhd" "" { Text "D:/CPU/ACC.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALU.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU-ALU_behave " "Info: Found design unit 1: ALU-ALU_behave" {  } { { "ALU.vhd" "" { Text "D:/CPU/ALU.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Info: Found entity 1: ALU" {  } { { "ALU.vhd" "" { Text "D:/CPU/ALU.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BR-BR_behave " "Info: Found design unit 1: BR-BR_behave" {  } { { "BR.vhd" "" { Text "D:/CPU/BR.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 BR " "Info: Found entity 1: BR" {  } { { "BR.vhd" "" { Text "D:/CPU/BR.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "C.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file C.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 C-C_behave " "Info: Found design unit 1: C-C_behave" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 C " "Info: Found entity 1: C" {  } { { "C.vhd" "" { Text "D:/CPU/C.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "IR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file IR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 IR-IR_behave " "Info: Found design unit 1: IR-IR_behave" {  } { { "IR.vhd" "" { Text "D:/CPU/IR.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 IR " "Info: Found entity 1: IR" {  } { { "IR.vhd" "" { Text "D:/CPU/IR.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MAR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file MAR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MAR-MAR_behave " "Info: Found design unit 1: MAR-MAR_behave" {  } { { "MAR.vhd" "" { Text "D:/CPU/MAR.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 MAR " "Info: Found entity 1: MAR" {  } { { "MAR.vhd" "" { Text "D:/CPU/MAR.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MBR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file MBR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MBR-MBR_behave " "Info: Found design unit 1: MBR-MBR_behave" {  } { { "MBR.vhd" "" { Text "D:/CPU/MBR.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 MBR " "Info: Found entity 1: MBR" {  } { { "MBR.vhd" "" { Text "D:/CPU/MBR.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PC-PC_behave " "Info: Found design unit 1: PC-PC_behave" {  } { { "PC.vhd" "" { Text "D:/CPU/PC.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 PC " "Info: Found entity 1: PC" {  } { { "PC.vhd" "" { Text "D:/CPU/PC.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CPU.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CPU.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CPU " "Info: Found entity 1: CPU" {  } { { "CPU.bdf" "" { Schematic "D:/CPU/CPU.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "change.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file change.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 change-change_behave " "Info: Found design unit 1: change-change_behave" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 change " "Info: Found entity 1: change" {  } { { "change.vhd" "" { Text "D:/CPU/change.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CPU " "Info: Elaborating entity \"CPU\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ACC ACC:inst4 " "Info: Elaborating entity \"ACC\" for hierarchy \"ACC:inst4\"" {  } { { "CPU.bdf" "inst4" { Schematic "D:/CPU/CPU.bdf" { { -192 1120 1320 -96 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom1.vhd 2 1 " "Warning: Using design file lpm_rom1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom1-SYN " "Info: Found design unit 1: lpm_rom1-SYN" {  } { { "lpm_rom1.vhd" "" { Text "D:/CPU/lpm_rom1.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom1 " "Info: Found entity 1: lpm_rom1" {  } { { "lpm_rom1.vhd" "" { Text "D:/CPU/lpm_rom1.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom1 lpm_rom1:inst10 " "Info: Elaborating entity \"lpm_rom1\" for hierarchy \"lpm_rom1:inst10\"" {  } { { "CPU.bdf" "inst10" { Schematic "D:/CPU/CPU.bdf" { { 88 1144 1304 152 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf" 43 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom1:inst10\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom1:inst10\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom1.vhd" "lpm_rom_component" { Text "D:/CPU/lpm_rom1.vhd" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom1:inst10\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"lpm_rom1:inst10\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom1.vhd" "" { Text "D:/CPU/lpm_rom1.vhd" 76 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/program files/quartus2/quartus/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/program files/quartus2/quartus/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/altrom.tdf" 77 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom1:inst10\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom1:inst10\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf" 60 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_rom1:inst10\|lpm_rom:lpm_rom_component\|altrom:srom lpm_rom1:inst10\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"lpm_rom1:inst10\|lpm_rom:lpm_rom_component\|altrom:srom\", which is child of megafunction instantiation \"lpm_rom1:inst10\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom.tdf" "" { Text "f:/program files/quartus2/quartus/libraries/megafunctions/lpm_rom.tdf" 60 3 0 } } { "lpm_rom1.vhd" "" { Text "D:/CPU/lpm_rom1.vhd" 76 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}