cpu.tan.rpt

实现简单CPU功能的源码

; N/A           ; None        ; -0.200 ns ; MUL_in[5]  ; MUL_OUT[5]$latch  ; C[25]    ;
; N/A           ; None        ; -0.200 ns ; MUL_in[21] ; MUL_OUT[5]$latch  ; C[25]    ;
; N/A           ; None        ; -0.300 ns ; MUL_in[27] ; MUL_OUT[11]$latch ; C[25]    ;
; N/A           ; None        ; -0.300 ns ; MUL_in[4]  ; MUL_OUT[4]$latch  ; C[25]    ;
; N/A           ; None        ; -0.400 ns ; MUL_in[25] ; MUL_OUT[9]$latch  ; C[25]    ;
; N/A           ; None        ; -0.400 ns ; MUL_in[8]  ; MUL_OUT[8]$latch  ; C[25]    ;
; N/A           ; None        ; -0.400 ns ; MUL_in[24] ; MUL_OUT[8]$latch  ; C[27]    ;
; N/A           ; None        ; -0.400 ns ; MUL_in[6]  ; MUL_OUT[6]$latch  ; C[25]    ;
; N/A           ; None        ; -0.400 ns ; MUL_in[20] ; MUL_OUT[4]$latch  ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; C[25]      ; MUL_OUT[1]$latch  ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; C[25]      ; MUL_OUT[2]$latch  ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; C[25]      ; MUL_OUT[12]$latch ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[31] ; MUL_OUT[15]$latch ; C[25]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[29] ; MUL_OUT[13]$latch ; C[25]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[11] ; MUL_OUT[11]$latch ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[10] ; MUL_OUT[10]$latch ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[26] ; MUL_OUT[10]$latch ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[9]  ; MUL_OUT[9]$latch  ; C[27]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[3]  ; MUL_OUT[3]$latch  ; C[25]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[1]  ; MUL_OUT[1]$latch  ; C[25]    ;
; N/A           ; None        ; -0.500 ns ; MUL_in[17] ; MUL_OUT[1]$latch  ; C[25]    ;
; N/A           ; None        ; -0.700 ns ; MUL_in[7]  ; MUL_OUT[7]$latch  ; C[27]    ;
; N/A           ; None        ; -0.700 ns ; MUL_in[23] ; MUL_OUT[7]$latch  ; C[27]    ;
; N/A           ; None        ; -0.700 ns ; MUL_in[22] ; MUL_OUT[6]$latch  ; C[27]    ;
; N/A           ; None        ; -0.700 ns ; MUL_in[5]  ; MUL_OUT[5]$latch  ; C[27]    ;
; N/A           ; None        ; -0.700 ns ; MUL_in[21] ; MUL_OUT[5]$latch  ; C[27]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[15] ; MUL_OUT[15]$latch ; C[25]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[14] ; MUL_OUT[14]$latch ; C[25]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[30] ; MUL_OUT[14]$latch ; C[25]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[13] ; MUL_OUT[13]$latch ; C[25]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[27] ; MUL_OUT[11]$latch ; C[27]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[4]  ; MUL_OUT[4]$latch  ; C[27]    ;
; N/A           ; None        ; -0.800 ns ; MUL_in[19] ; MUL_OUT[3]$latch  ; C[25]    ;
; N/A           ; None        ; -0.900 ns ; MUL_in[25] ; MUL_OUT[9]$latch  ; C[27]    ;
; N/A           ; None        ; -0.900 ns ; MUL_in[8]  ; MUL_OUT[8]$latch  ; C[27]    ;
; N/A           ; None        ; -0.900 ns ; MUL_in[6]  ; MUL_OUT[6]$latch  ; C[27]    ;
; N/A           ; None        ; -1.000 ns ; MUL_in[31] ; MUL_OUT[15]$latch ; C[27]    ;
; N/A           ; None        ; -1.000 ns ; MUL_in[29] ; MUL_OUT[13]$latch ; C[27]    ;
; N/A           ; None        ; -1.000 ns ; MUL_in[3]  ; MUL_OUT[3]$latch  ; C[27]    ;
; N/A           ; None        ; -1.000 ns ; MUL_in[1]  ; MUL_OUT[1]$latch  ; C[27]    ;
; N/A           ; None        ; -1.000 ns ; MUL_in[17] ; MUL_OUT[1]$latch  ; C[27]    ;
; N/A           ; None        ; -1.300 ns ; MUL_in[15] ; MUL_OUT[15]$latch ; C[27]    ;
; N/A           ; None        ; -1.300 ns ; MUL_in[14] ; MUL_OUT[14]$latch ; C[27]    ;
; N/A           ; None        ; -1.300 ns ; MUL_in[30] ; MUL_OUT[14]$latch ; C[27]    ;
; N/A           ; None        ; -1.300 ns ; MUL_in[13] ; MUL_OUT[13]$latch ; C[27]    ;
; N/A           ; None        ; -1.300 ns ; MUL_in[19] ; MUL_OUT[3]$latch  ; C[27]    ;
; N/A           ; None        ; -2.500 ns ; MUL_in[18] ; MUL_OUT[2]$latch  ; C[25]    ;
; N/A           ; None        ; -2.800 ns ; MUL_in[12] ; MUL_OUT[12]$latch ; C[25]    ;
; N/A           ; None        ; -2.800 ns ; MUL_in[28] ; MUL_OUT[12]$latch ; C[25]    ;
; N/A           ; None        ; -2.800 ns ; MUL_in[2]  ; MUL_OUT[2]$latch  ; C[25]    ;
; N/A           ; None        ; -3.000 ns ; MUL_in[18] ; MUL_OUT[2]$latch  ; C[27]    ;
; N/A           ; None        ; -3.300 ns ; MUL_in[12] ; MUL_OUT[12]$latch ; C[27]    ;
; N/A           ; None        ; -3.300 ns ; MUL_in[28] ; MUL_OUT[12]$latch ; C[27]    ;
; N/A           ; None        ; -3.300 ns ; MUL_in[2]  ; MUL_OUT[2]$latch  ; C[27]    ;
+---------------+-------------+-----------+------------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Apr 27 13:05:15 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CPU -c CPU
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "MUL_OUT[0]$latch" is a latch
    Warning: Node "MUL_OUT[1]$latch" is a latch
    Warning: Node "MUL_OUT[2]$latch" is a latch
    Warning: Node "MUL_OUT[3]$latch" is a latch
    Warning: Node "MUL_OUT[4]$latch" is a latch
    Warning: Node "MUL_OUT[5]$latch" is a latch
    Warning: Node "MUL_OUT[6]$latch" is a latch
    Warning: Node "MUL_OUT[7]$latch" is a latch
    Warning: Node "MUL_OUT[8]$latch" is a latch
    Warning: Node "MUL_OUT[9]$latch" is a latch
    Warning: Node "MUL_OUT[10]$latch" is a latch
    Warning: Node "MUL_OUT[11]$latch" is a latch
    Warning: Node "MUL_OUT[12]$latch" is a latch
    Warning: Node "MUL_OUT[13]$latch" is a latch
    Warning: Node "MUL_OUT[14]$latch" is a latch
    Warning: Node "MUL_OUT[15]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "C[27]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "C[25]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "MUL_OUT[15]~16" as buffer
Info: tsu for register "MUL_OUT[12]$latch" (data pin = "MUL_in[12]", clock pin = "C[27]") is 7.200 ns
    Info: + Longest pin to register delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'MUL_in[12]'
        Info: 2: + IC(2.700 ns) + CELL(1.900 ns) = 7.700 ns; Loc. = LC6_B20; Fanout = 1; COMB Node = 'MUL_OUT[12]~77'
        Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 10.200 ns; Loc. = LC8_B20; Fanout = 1; REG Node = 'MUL_OUT[12]$latch'
        Info: Total cell delay = 6.900 ns ( 67.65 % )
        Info: Total interconnect delay = 3.300 ns ( 32.35 % )
    Info: + Micro setup delay of destination is 3.900 ns
    Info: - Shortest clock path from clock "C[27]" to destination register is 6.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_56; Fanout = 1; CLK Node = 'C[27]'
        Info: 2: + IC(1.600 ns) + CELL(1.400 ns) = 4.900 ns; Loc. = LC3_B20; Fanout = 16; COMB Node = 'MUL_OUT[15]~16'
        Info: 3: + IC(0.600 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC8_B20; Fanout = 1; REG Node = 'MUL_OUT[12]$latch'
        Info: Total cell delay = 4.700 ns ( 68.12 % )
        Info: Total interconnect delay = 2.200 ns ( 31.88 % )
Info: tco from clock "C[25]" to destination pin "MUL_OUT[9]" through register "MUL_OUT[9]$latch" is 16.200 ns
    Info: + Longest clock path from clock "C[25]" to source register is 10.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'C[25]'
        Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC3_B20; Fanout = 16; COMB Node = 'MUL_OUT[15]~16'
        Info: 3: + IC(3.300 ns) + CELL(1.400 ns) = 10.100 ns; Loc. = LC6_A14; Fanout = 1; REG Node = 'MUL_OUT[9]$latch'
        Info: Total cell delay = 5.200 ns ( 51.49 % )
        Info: Total interconnect delay = 4.900 ns ( 48.51 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A14; Fanout = 1; REG Node = 'MUL_OUT[9]$latch'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'MUL_OUT[9]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: th for register "MUL_OUT[4]$latch" (data pin = "C[25]", clock pin = "C[25]") is 2.500 ns
    Info: + Longest clock path from clock "C[25]" to destination register is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'C[25]'
        Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC3_B20; Fanout = 16; COMB Node = 'MUL_OUT[15]~16'
        Info: 3: + IC(3.200 ns) + CELL(1.400 ns) = 10.000 ns; Loc. = LC3_A19; Fanout = 1; REG Node = 'MUL_OUT[4]$latch'
        Info: Total cell delay = 5.200 ns ( 52.00 % )
        Info: Total interconnect delay = 4.800 ns ( 48.00 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 17; CLK Node = 'C[25]'
        Info: 2: + IC(1.700 ns) + CELL(1.400 ns) = 5.000 ns; Loc. = LC1_A19; Fanout = 1; COMB Node = 'MUL_OUT[4]~69'
        Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 7.500 ns; Loc. = LC3_A19; Fanout = 1; REG Node = 'MUL_OUT[4]$latch'
        Info: Total cell delay = 5.200 ns ( 69.33 % )
        Info: Total interconnect delay = 2.300 ns ( 30.67 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 19 warnings
    Info: Allocated 105 megabytes of memory during processing
    Info: Processing ended: Sun Apr 27 13:05:15 2008
    Info: Elapsed time: 00:00:00