change.vhd

实现简单CPU功能的源码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity change is
port(
     clk: in std_logic;
     MUL_in: in std_logic_vector(31 downto 0);
     C: in std_logic_vector(31 downto 0);
     MUL_OUT: out std_logic_vector(15 downto 0)
);
end change;
architecture change_behave of change is
begin
  process(clk)
   begin
    if C(25)='1' then 
     MUL_OUT<=MUL_in(31 downto 16);
    elsif C(27)='1' then
   MUL_OUT<=MUL_in(15 downto 0);
    end if;
  end process;
end change_behave;