📄 div8.tan.rpt
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Classic Timing Analyzer report for div8
Tue May 12 10:56:37 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 7.285 ns ; temp[2] ; clk_out ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[2] ; temp[2] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+---------+---------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[2] ; temp[2] ; clk ; clk ; None ; None ; 1.980 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[1] ; temp[2] ; clk ; clk ; None ; None ; 1.772 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[1] ; temp[1] ; clk ; clk ; None ; None ; 1.762 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[0] ; temp[1] ; clk ; clk ; None ; None ; 1.542 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[0] ; temp[2] ; clk ; clk ; None ; None ; 1.534 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; temp[0] ; temp[0] ; clk ; clk ; None ; None ; 1.531 ns ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------+---------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------+---------+------------+
; N/A ; None ; 7.285 ns ; temp[2] ; clk_out ; clk ;
+-------+--------------+------------+---------+---------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue May 12 10:56:36 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div8 -c div8
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "temp[2]" and destination register "temp[2]"
Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.980 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y10_N2; Fanout = 2; REG Node = 'temp[2]'
Info: 2: + IC(0.919 ns) + CELL(1.061 ns) = 1.980 ns; Loc. = LC_X5_Y10_N2; Fanout = 2; REG Node = 'temp[2]'
Info: Total cell delay = 1.061 ns ( 53.59 % )
Info: Total interconnect delay = 0.919 ns ( 46.41 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y10_N2; Fanout = 2; REG Node = 'temp[2]'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: - Longest clock path from clock "clk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y10_N2; Fanout = 2; REG Node = 'temp[2]'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "clk_out" through register "temp[2]" is 7.285 ns
Info: + Longest clock path from clock "clk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 3; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X5_Y10_N2; Fanout = 2; REG Node = 'temp[2]'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Longest register to pin delay is 3.090 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y10_N2; Fanout = 2; REG Node = 'temp[2]'
Info: 2: + IC(0.768 ns) + CELL(2.322 ns) = 3.090 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'clk_out'
Info: Total cell delay = 2.322 ns ( 75.15 % )
Info: Total interconnect delay = 0.768 ns ( 24.85 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 148 megabytes of memory during processing
Info: Processing ended: Tue May 12 10:56:38 2009
Info: Elapsed time: 00:00:02
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