div8.vhd

来自「分频系数为8」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY div8 IS
	PORT(
		clk,clear: IN STD_LOGIC;
		clk_out: OUT STD_LOGIC);
END div8;

ARCHITECTURE div8_arch OF div8 IS
	SIGNAL temp: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
	PROCESS(clear,clk)
	BEGIN
		IF clear = '0' THEN
			temp <= "000";
		ELSIF (clk'event and clk='1') THEN
			temp <= temp + 1;
		END IF;
	END PROCESS;
	clk_out <= temp(2);
END div8_arch;